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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.22 2002/04/24 08:52:19 mohor
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// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
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// bug fixed.
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//
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// Revision 1.21 2002/03/29 16:18:11 lampret
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// Revision 1.21 2002/03/29 16:18:11 lampret
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// Small typo fixed.
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// Small typo fixed.
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//
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//
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// Revision 1.20 2002/03/25 16:19:12 mohor
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// Revision 1.20 2002/03/25 16:19:12 mohor
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// Any address can be used for Tx and Rx BD pointers. Address does not need
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// Any address can be used for Tx and Rx BD pointers. Address does not need
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| Line 360... |
Line 364... |
wire [7:0] TempRxBDAddress;
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wire [7:0] TempRxBDAddress;
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wire SetGotData;
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wire SetGotData;
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wire GotDataEvaluate;
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wire GotDataEvaluate;
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reg temp_ack;
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reg WB_ACK_O;
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wire [6:0] RxStatusIn;
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wire [6:0] RxStatusIn;
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reg [6:0] RxStatusInLatched;
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reg [6:0] RxStatusInLatched;
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`ifdef ETH_REGISTERED_OUTPUTS
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reg temp_ack2;
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reg [31:0] registered_ram_do;
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`endif
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reg WbEn, WbEn_q;
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reg WbEn, WbEn_q;
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reg RxEn, RxEn_q;
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reg RxEn, RxEn_q;
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reg TxEn, TxEn_q;
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reg TxEn, TxEn_q;
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wire ram_ce;
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wire ram_ce;
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| Line 394... |
Line 393... |
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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temp_ack <=#Tp 1'b0;
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WB_ACK_O <=#Tp 1'b0;
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`ifdef ETH_REGISTERED_OUTPUTS
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temp_ack2 <=#Tp 1'b0;
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registered_ram_do <=#Tp 32'h0;
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`endif
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end
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end
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else
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else
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begin
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begin
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temp_ack <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
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WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
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`ifdef ETH_REGISTERED_OUTPUTS
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temp_ack2 <=#Tp temp_ack;
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registered_ram_do <=#Tp ram_do;
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`endif
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end
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end
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end
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end
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`ifdef ETH_REGISTERED_OUTPUTS
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assign WB_ACK_O = temp_ack2;
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assign WB_DAT_O = registered_ram_do;
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`else
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assign WB_ACK_O = temp_ack;
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assign WB_DAT_O = ram_do;
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assign WB_DAT_O = ram_do;
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`endif
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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generic_spram #(8, 32) ram (
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generic_spram #(8, 32) ram (
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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| Line 442... |
Line 426... |
else
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else
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if(TxPointerRead & TxEn & TxEn_q)
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if(TxPointerRead & TxEn & TxEn_q)
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TxEn_needed <=#Tp 1'b0;
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TxEn_needed <=#Tp 1'b0;
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end
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end
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reg [3:0] stm_status;
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// Enabling access to the RAM for three devices.
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// Enabling access to the RAM for three devices.
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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| Line 455... |
Line 439... |
TxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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ram_addr <=#Tp 8'h0;
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ram_addr <=#Tp 8'h0;
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ram_di <=#Tp 32'h0;
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ram_di <=#Tp 32'h0;
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BDRead <=#Tp 1'b0;
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BDRead <=#Tp 1'b0;
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BDWrite <=#Tp 1'b0;
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BDWrite <=#Tp 1'b0;
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stm_status <=#Tp 4'h0;
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end
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end
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else
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else
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begin
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begin
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// Switching between three stages depends on enable signals
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// Switching between three stages depends on enable signals
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case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
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case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
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5'b100_10, 5'b100_11 :
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5'b100_10, 5'b100_11 :
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begin
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begin
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stm_status <=#Tp 4'h1;
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WbEn <=#Tp 1'b0;
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WbEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
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RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
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TxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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ram_addr <=#Tp RxBDAddress + RxPointerRead;
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ram_addr <=#Tp RxBDAddress + RxPointerRead;
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ram_di <=#Tp RxBDDataIn;
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ram_di <=#Tp RxBDDataIn;
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end
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end
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5'b100_01 :
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5'b100_01 :
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begin
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begin
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stm_status <=#Tp 4'h2;
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WbEn <=#Tp 1'b0;
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WbEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
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TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
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ram_addr <=#Tp TxBDAddress + TxPointerRead;
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ram_addr <=#Tp TxBDAddress + TxPointerRead;
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ram_di <=#Tp TxBDDataIn;
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ram_di <=#Tp TxBDDataIn;
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end
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end
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5'b010_00, 5'b010_10 :
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5'b010_00, 5'b010_10 :
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begin
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begin
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stm_status <=#Tp 4'h3;
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WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
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WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
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RxEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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ram_addr <=#Tp WB_ADR_I[9:2];
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ram_addr <=#Tp WB_ADR_I[9:2];
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ram_di <=#Tp WB_DAT_I;
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ram_di <=#Tp WB_DAT_I;
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BDWrite <=#Tp BDCs & WB_WE_I;
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BDWrite <=#Tp BDCs & WB_WE_I;
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BDRead <=#Tp BDCs & ~WB_WE_I;
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BDRead <=#Tp BDCs & ~WB_WE_I;
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end
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end
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5'b010_01, 5'b010_11 :
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5'b010_01, 5'b010_11 :
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begin
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begin
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stm_status <=#Tp 4'h4;
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WbEn <=#Tp 1'b0;
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WbEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
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TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
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ram_addr <=#Tp TxBDAddress + TxPointerRead;
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ram_addr <=#Tp TxBDAddress + TxPointerRead;
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ram_di <=#Tp TxBDDataIn;
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ram_di <=#Tp TxBDDataIn;
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end
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end
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5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
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5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
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begin
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begin
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stm_status <=#Tp 4'h5;
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WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
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WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
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RxEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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ram_addr <=#Tp WB_ADR_I[9:2];
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ram_addr <=#Tp WB_ADR_I[9:2];
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ram_di <=#Tp WB_DAT_I;
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ram_di <=#Tp WB_DAT_I;
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BDWrite <=#Tp BDCs & WB_WE_I;
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BDWrite <=#Tp BDCs & WB_WE_I;
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BDRead <=#Tp BDCs & ~WB_WE_I;
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BDRead <=#Tp BDCs & ~WB_WE_I;
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end
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end
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5'b100_00 :
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5'b100_00 :
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begin
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begin
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stm_status <=#Tp 4'h6;
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WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
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WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
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end
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end
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5'b000_00 :
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5'b000_00 :
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begin
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begin
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stm_status <=#Tp 4'h7;
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WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
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WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
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RxEn <=#Tp 1'b0;
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RxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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TxEn <=#Tp 1'b0;
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ram_addr <=#Tp WB_ADR_I[9:2];
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ram_addr <=#Tp WB_ADR_I[9:2];
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ram_di <=#Tp WB_DAT_I;
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ram_di <=#Tp WB_DAT_I;
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