| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.7 2002/10/18 13:58:22 tadejm
|
|
// Some code changed due to bug fixes.
|
|
//
|
// Revision 1.6 2002/10/09 13:16:51 tadejm
|
// Revision 1.6 2002/10/09 13:16:51 tadejm
|
// Just back-up; not completed testbench and some testcases are not
|
// Just back-up; not completed testbench and some testcases are not
|
// wotking properly yet.
|
// wotking properly yet.
|
//
|
//
|
// Revision 1.5 2002/09/18 17:55:08 tadej
|
// Revision 1.5 2002/09/18 17:55:08 tadej
|
| Line 208... |
Line 211... |
#1 $fdisplay(phy_log, " (%0t)(%m)PHY configured tp 10 Mbps!", $time);
|
#1 $fdisplay(phy_log, " (%0t)(%m)PHY configured tp 10 Mbps!", $time);
|
end
|
end
|
`endif
|
`endif
|
|
|
// different clock calculation between RX and TX, so that there is alsways a litle difference
|
// different clock calculation between RX and TX, so that there is alsways a litle difference
|
|
/*initial
|
|
begin
|
|
set_mrx_equal_mtx = 1; // default
|
|
end*/
|
|
|
always
|
always
|
begin
|
begin
|
mtx_clk_o = 0;
|
mtx_clk_o = 0;
|
#7;
|
#7;
|
forever
|
forever
|
| Line 227... |
Line 235... |
end
|
end
|
end
|
end
|
|
|
always
|
always
|
begin
|
begin
|
mrx_clk_o = 1;
|
// EQUAL mrx_clk to mtx_clk
|
#3;
|
mrx_clk_o = 0;
|
|
#7;
|
forever
|
forever
|
begin
|
begin
|
if (status_bit6_0[2]) // Link is UP
|
|
begin
|
|
if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
|
if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
|
begin
|
begin
|
//#(((1/0.025001)/2))
|
#20 mrx_clk_o = ~mrx_clk_o;
|
#19.99 mrx_clk_o = ~mrx_clk_o; // period is calculated from frequency in GHz
|
|
end
|
end
|
else // 10 Mbps - 2.5 MHz, 400 ns
|
else // 10 Mbps - 2.5 MHz, 400 ns
|
begin
|
begin
|
//#(((1/0.0024999)/2))
|
#200 mrx_clk_o = ~mrx_clk_o;
|
#200.01 mrx_clk_o = ~mrx_clk_o; // period is calculated from frequency in GHz
|
|
end
|
|
end
|
|
else // Link is down
|
|
begin
|
|
#(rx_link_down_halfperiod) mrx_clk_o = ~mrx_clk_o; // random frequency between 2 MHz and 40 MHz
|
|
end
|
end
|
end
|
end
|
|
// DIFFERENT mrx_clk than mtx_clk
|
|
/* mrx_clk_diff_than_mtx = 1;
|
|
#3;
|
|
forever
|
|
begin
|
|
if (status_bit6_0[2]) // Link is UP
|
|
begin
|
|
if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
|
|
begin
|
|
//#(((1/0.025001)/2))
|
|
#19.99 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz
|
|
end
|
|
else // 10 Mbps - 2.5 MHz, 400 ns
|
|
begin
|
|
//#(((1/0.0024999)/2))
|
|
#200.01 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz
|
|
end
|
|
end
|
|
else // Link is down
|
|
begin
|
|
#(rx_link_down_halfperiod) mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // random frequency between 2 MHz and 40 MHz
|
|
end
|
|
end*/
|
|
// // set output mrx_clk
|
|
// if (set_mrx_equal_mtx)
|
|
// mrx_clk_o = mrx_clk_equal_to_mtx;
|
|
// else
|
|
// mrx_clk_o = mrx_clk_diff_than_mtx;
|
end
|
end
|
|
|
|
// set output mrx_clk
|
|
//assign mrx_clk_o = set_mrx_equal_mtx ? mrx_clk_equal_to_mtx : mrx_clk_diff_than_mtx ;
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// PHY management (MIIM) interface
|
// PHY management (MIIM) interface
|
//
|
//
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
| Line 688... |
Line 719... |
|
|
// wholy writable registers for walking ONE's on data, phy and reg. addresses
|
// wholy writable registers for walking ONE's on data, phy and reg. addresses
|
reg registers_addr_data_test_operation;
|
reg registers_addr_data_test_operation;
|
|
|
// Non writable status registers
|
// Non writable status registers
|
always
|
initial // always
|
begin
|
begin
|
#1 status_bit6_0[6] = no_preamble;
|
#1 status_bit6_0[6] = no_preamble;
|
status_bit6_0[5] = 1'b0;
|
status_bit6_0[5] = 1'b0;
|
status_bit6_0[3] = 1'b1;
|
status_bit6_0[3] = 1'b1;
|
status_bit6_0[0] = 1'b1;
|
status_bit6_0[0] = 1'b1;
|
| Line 827... |
Line 858... |
// Internal signals controling Carrier sense & Collision
|
// Internal signals controling Carrier sense & Collision
|
// MAC common signals generated when appropriate transfer
|
// MAC common signals generated when appropriate transfer
|
reg mcrs_rx;
|
reg mcrs_rx;
|
reg mcrs_tx;
|
reg mcrs_tx;
|
// delayed mtxen_i signal for generating delayed tx carrier sense
|
// delayed mtxen_i signal for generating delayed tx carrier sense
|
reg mtxen_d;
|
reg mtxen_d1;
|
|
reg mtxen_d2;
|
|
reg mtxen_d3;
|
|
reg mtxen_d4;
|
|
reg mtxen_d5;
|
|
reg mtxen_d6;
|
// collision signal set or rest within task for controling collision
|
// collision signal set or rest within task for controling collision
|
reg task_mcoll;
|
reg task_mcoll;
|
// carrier sense signal set or rest within task for controling carrier sense
|
// carrier sense signal set or rest within task for controling carrier sense
|
reg task_mcrs;
|
reg task_mcrs;
|
reg task_mcrs_lost;
|
reg task_mcrs_lost;
|
| Line 1056... |
Line 1092... |
|
|
// generating CARRIER SENSE for TX with or without delay
|
// generating CARRIER SENSE for TX with or without delay
|
if (!m_rst_n_i)
|
if (!m_rst_n_i)
|
begin
|
begin
|
mcrs_tx <= 0;
|
mcrs_tx <= 0;
|
mtxen_d <= 0;
|
mtxen_d1 <= 0;
|
|
mtxen_d2 <= 0;
|
|
mtxen_d3 <= 0;
|
|
mtxen_d4 <= 0;
|
|
mtxen_d5 <= 0;
|
|
mtxen_d6 <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (!real_carrier_sense)
|
mtxen_d1 <= mtxen_i;
|
begin
|
mtxen_d2 <= mtxen_d1;
|
mtxen_d <= mtxen_i;
|
mtxen_d3 <= mtxen_d2;
|
mcrs_tx <= mtxen_i;
|
mtxen_d4 <= mtxen_d3;
|
end
|
mtxen_d5 <= mtxen_d4;
|
|
mtxen_d6 <= mtxen_d5;
|
|
if (real_carrier_sense)
|
|
mcrs_tx <= mtxen_d6;
|
else
|
else
|
begin
|
mcrs_tx <= mtxen_i;
|
mtxen_d <= mtxen_i;
|
|
mcrs_tx <= mtxen_d;
|
|
end
|
|
end
|
end
|
end
|
end
|
|
|
`ifdef VERBOSE
|
`ifdef VERBOSE
|
reg frame_started;
|
reg frame_started;
|
