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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Diff between revs 17 and 19

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2001/08/15 14:04:30  mohor
 
// Signal names changed on the top level for easier pad insertion (ASIC).
 
//
// Revision 1.1  2001/08/06 14:41:09  mohor
// Revision 1.1  2001/08/06 14:41:09  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// File eth_timescale.v is used to define timescale
Line 127... Line 130...
        .wb_adr_i(WB_ADR_I), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
        .wb_adr_i(WB_ADR_I), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
        .wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
        .wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
        .wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
        .wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
 
 
  //TX
  //TX
  .mtxclk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
 
 
  //RX
  //RX
  .mrxclk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
 
 
  // MIIM
  // MIIM
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_pad_oe(Mdo_OE)
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE)
);
);
 
 
 
 
 
 
 
 
Line 146... Line 149...
 
 
 
 
initial
initial
begin
begin
  WB_CLK_I  =  1'b0;
  WB_CLK_I  =  1'b0;
  WB_DAT_I  = 32'hx;
  WB_DAT_I  = 32'h0;
  WB_ADR_I  = 32'hx;
  WB_ADR_I  = 32'h0;
  WB_SEL_I  =  4'hx;
  WB_SEL_I  =  4'h0;
  WB_WE_I   =  1'bx;
  WB_WE_I   =  1'b0;
  WB_CYC_I  =  1'b0;
  WB_CYC_I  =  1'b0;
  WB_STB_I  =  1'b0;
  WB_STB_I  =  1'b0;
  WB_ACK_I  =  2'h0;
  WB_ACK_I  =  2'h0;
  MTxClk    =  1'b0;
  MTxClk    =  1'b0;
  MRxClk    =  1'b0;
  MRxClk    =  1'b0;
Line 171... Line 174...
 
 
 
 
// Reset pulse
// Reset pulse
initial
initial
begin
begin
  GSR           =  1'b0;
  GSR           =  1'b1;
  WB_RST_I      =  1'b0;
  WB_RST_I      =  1'b1;
  #100 WB_RST_I =  1'b1;
  #100 WB_RST_I =  1'b1;
  GSR           =  1'b1;
  GSR           =  1'b1;
  #100 WB_RST_I =  1'b0;
  #100 WB_RST_I =  1'b0;
  GSR           =  1'b0;
  GSR           =  1'b0;
  #100 StartTB  =  1'b1;
  #100 StartTB  =  1'b1;
Line 188... Line 191...
 
 
 
 
// Generating WB_CLK_I clock
// Generating WB_CLK_I clock
always
always
begin
begin
 
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
//  forever #100 WB_CLK_I = ~WB_CLK_I;
//  forever #100 WB_CLK_I = ~WB_CLK_I;
end
end
Line 214... Line 218...
 
 
initial
initial
begin
begin
  wait(StartTB);  // Start of testbench
  wait(StartTB);  // Start of testbench
 
 
  WishboneWrite(32'h00000800, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2});    // r_Rst = 1
  WishboneWrite(32'h00000800, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2});    // r_Rst = 1
  WishboneWrite(32'h00000000, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2});    // r_Rst = 0
  WishboneWrite(32'h00000000, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2});    // r_Rst = 0
  WishboneWrite(32'h00000080, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `RX_BD_ADR_ADR<<2});// r_RxBDAddress = 0x80
  WishboneWrite(32'h00000080, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_RX_BD_ADR_ADR<<2});// r_RxBDAddress = 0x80
  WishboneWrite(32'h0002A443, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2});    // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
  WishboneWrite(32'h0002A443, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2});    // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
  WishboneWrite(32'h00000004, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `CTRLMODER_ADR<<2});//r_TxFlow = 1
  WishboneWrite(32'h00000004, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_CTRLMODER_ADR<<2});//r_TxFlow = 1
 
 
 
 
 
 
 
 
  SendPacket(16'h0015, 1'b0);
  SendPacket(16'h0015, 1'b0);
Line 237... Line 241...
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
 
 
  WishboneRead({`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2});   // Read from MODER register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2});   // Read from MODER register
 
 
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h0<<2)});       // Read from TxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h0<<2)});       // Read from TxBD register
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h1<<2)});       // Read from TxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h1<<2)});       // Read from TxBD register
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h2<<2)});       // Read from TxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h2<<2)});       // Read from TxBD register
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h3<<2)});       // Read from TxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h3<<2)});       // Read from TxBD register
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h4<<2)});       // Read from TxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h4<<2)});       // Read from TxBD register
 
 
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h80<<2)});       // Read from RxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h80<<2)});       // Read from RxBD register
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h81<<2)});       // Read from RxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h81<<2)});       // Read from RxBD register
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h82<<2)});       // Read from RxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h82<<2)});       // Read from RxBD register
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h83<<2)});       // Read from RxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h83<<2)});       // Read from RxBD register
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h84<<2)});       // Read from RxBD register
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h84<<2)});       // Read from RxBD register
 
 
  #10000 $stop;
  #10000 $stop;
end
end
 
 
 
 
Line 277... Line 281...
    WB_WE_I  = 1'b1;
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
    WB_SEL_I = 4'hf;
 
 
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
//    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
    begin
//    begin
      @ (posedge WB_CLK_I);
//      @ (posedge WB_CLK_I);
    end
//    end
 
 
 
//    if(ii==20)
 
//      begin
 
//        $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)", 
 
//          Data, Address, $time);
 
//        #50 $stop;
 
//      end
 
 
    if(ii==20)
    wait(WB_ACK_O);   // waiting for acknowledge response
      begin
 
        $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
 
          Data, Address, $time);
 
        #50 $stop;
 
      end
 
 
 
 
    // Writing information about the access to the screen
    @ (posedge WB_CLK_I);
    @ (posedge WB_CLK_I);
    if(Address[31:16] == `ETHERNET_SPACE)
    if(Address[31:16] == `ETH_ETHERNET_SPACE)
      if(Address[15:12] == `REG_SPACE)
      if(Address[15:12] == `ETH_REG_SPACE)
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
      else
      else
      if(Address[15:12] == `BD_SPACE)
      if(Address[15:12] == `ETH_BD_SPACE)
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
          begin
          begin
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address[9:2]);
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address[9:2]);
            if(Data[13])
            if(Data[13])
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
Line 349... Line 356...
          Address, $time);
          Address, $time);
        #50 $stop;
        #50 $stop;
      end
      end
 
 
    @ (posedge WB_CLK_I);
    @ (posedge WB_CLK_I);
    if(Address[31:16] == `ETHERNET_SPACE)
    if(Address[31:16] == `ETH_ETHERNET_SPACE)
      if(Address[15:12] == `REG_SPACE)
      if(Address[15:12] == `ETH_REG_SPACE)
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
      else
      else
      if(Address[15:12] == `BD_SPACE)
      if(Address[15:12] == `ETH_BD_SPACE)
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
          begin
          begin
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address[9:2]);
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address[9:2]);
          end
          end
        else
        else
Line 390... Line 397...
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
      Wrap = 1'b1;
      Wrap = 1'b1;
    else
    else
      Wrap = 1'b0;
      Wrap = 1'b0;
 
 
    TempAddr = {`ETHERNET_SPACE, `BD_SPACE, 2'h0, (TxBDIndex<<2)};
    TempAddr = {`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (TxBDIndex<<2)};
    TempData = {Length[15:0], 1'b1, Wrap, ControlFrame, 5'h0, TxBDIndex[7:0]};  // Ready and Wrap = 1
    TempData = {Length[15:0], 1'b1, Wrap, ControlFrame, 5'h0, TxBDIndex[7:0]};  // Ready and Wrap = 1
 
 
    #1;
    #1;
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
      TxBDIndex = 0;
      TxBDIndex = 0;
Line 427... Line 434...
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
      WrapRx = 1'b1;
      WrapRx = 1'b1;
    else
    else
      WrapRx = 1'b0;
      WrapRx = 1'b0;
 
 
    TempRxAddr = {`ETHERNET_SPACE, `BD_SPACE, 2'h0, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
    TempRxAddr = {`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
 
 
    TempRxData = {LengthRx[15:0], 1'b1, WrapRx, 6'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
    TempRxData = {LengthRx[15:0], 1'b1, WrapRx, 6'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
 
 
    #1;
    #1;
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
Line 480... Line 487...
 
 
    wait (~WishboneBusy);
    wait (~WishboneBusy);
    WishboneBusy = 1;
    WishboneBusy = 1;
    #1;
    #1;
    WB_DAT_I = {a, b, c, d};
    WB_DAT_I = {a, b, c, d};
    WB_ADR_I = {`ETHERNET_SPACE, `TX_DATA, pp[11:0]};
    WB_ADR_I = {`ETH_ETHERNET_SPACE, `ETH_TX_DATA, pp[11:0]};
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
 
 
    WB_WE_I  = 1'b1;
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_STB_I = 1'b1;
Line 516... Line 523...
    repeat(Delay) @(posedge WB_CLK_I);
    repeat(Delay) @(posedge WB_CLK_I);
 
 
    wait (~WishboneBusy);
    wait (~WishboneBusy);
    WishboneBusy = 1;
    WishboneBusy = 1;
    #1;
    #1;
    WB_ADR_I = {`ETHERNET_SPACE, `RX_DATA, rr[11:0]};
    WB_ADR_I = {`ETH_ETHERNET_SPACE, `ETH_RX_DATA, rr[11:0]};
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
 
 
    WB_WE_I  = 1'b1;
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_STB_I = 1'b1;

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