| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/10/19 08:46:53 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.3 2001/09/24 14:55:49 mohor
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// Revision 1.3 2001/09/24 14:55:49 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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// demands).
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| Line 131... |
Line 135... |
(
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(
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// WISHBONE common
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// WISHBONE common
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.wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
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.wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
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// WISHBONE slave
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// WISHBONE slave
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.wb_adr_i(WB_ADR_I), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
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.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
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.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
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.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
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.wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),
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.wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),
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//TX
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//TX
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.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
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.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
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| Line 251... |
Line 255... |
ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
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WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
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WishboneRead({24'h100, (8'h0<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h1<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h2<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h3<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h4<<2)}); // Read from TxBD register
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WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register
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WishboneRead({22'h40, (10'h80<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h81<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h82<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h83<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h83<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h84<<2)}); // Read from RxBD register
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WishboneRead({22'h01, (10'h84<<2)}); // Read from RxBD register
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#10000 $stop;
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#10000 $stop;
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end
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end
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| Line 305... |
Line 309... |
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wait(WB_ACK_O); // waiting for acknowledge response
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wait(WB_ACK_O); // waiting for acknowledge response
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// Writing information about the access to the screen
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// Writing information about the access to the screen
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@ (posedge WB_CLK_I);
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@ (posedge WB_CLK_I);
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if(~Address[17] & ~Address[16])
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if(~Address[11] & ~Address[10])
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$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
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$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
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else
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else
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if(~Address[17] & Address[16])
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if(~Address[11] & Address[10])
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if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
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if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
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begin
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begin
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$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
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$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
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if(Data[13])
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if(Data[9])
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$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
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$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
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end
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end
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else
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else
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$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
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$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
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else
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else
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| Line 361... |
Line 365... |
Address, $time);
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Address, $time);
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#50 $stop;
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#50 $stop;
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end
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end
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@ (posedge WB_CLK_I);
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@ (posedge WB_CLK_I);
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if(~Address[17] & ~Address[16])
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if(~Address[11] & ~Address[10])
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$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
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$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
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else
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else
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if(~Address[17] & Address[16])
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if(~Address[11] & Address[10])
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if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
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if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
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begin
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begin
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$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
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$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
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end
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end
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else
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else
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| Line 399... |
Line 403... |
if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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Wrap = 1'b1;
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Wrap = 1'b1;
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else
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else
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Wrap = 1'b0;
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Wrap = 1'b0;
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TempAddr = {22'h40, (TxBDIndex<<2)};
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TempAddr = {22'h01, (TxBDIndex<<2)};
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TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
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TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
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#1;
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#1;
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if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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TxBDIndex = 0;
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TxBDIndex = 0;
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| Line 436... |
Line 440... |
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
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if(RxBDIndex == 3) // Only 4 buffer descriptors are used
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WrapRx = 1'b1;
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WrapRx = 1'b1;
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else
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else
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WrapRx = 1'b0;
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WrapRx = 1'b0;
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TempRxAddr = {22'h40, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
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TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
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TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
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TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
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#1;
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#1;
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if(RxBDIndex == 3) // Only 4 buffer descriptors are used
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if(RxBDIndex == 3) // Only 4 buffer descriptors are used
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| Line 489... |
Line 493... |
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wait (~WishboneBusy);
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wait (~WishboneBusy);
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WishboneBusy = 1;
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WishboneBusy = 1;
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#1;
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#1;
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WB_DAT_I = {a, b, c, d};
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WB_DAT_I = {a, b, c, d};
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WB_ADR_I = {20'h20, pp[11:0]};
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// WB_ADR_I = {20'h20, pp[11:0]};
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WB_ADR_I = {22'h02, pp[9:0]};
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$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
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$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
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WB_WE_I = 1'b1;
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WB_WE_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_STB_I = 1'b1;
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WB_STB_I = 1'b1;
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| Line 525... |
Line 530... |
repeat(Delay) @(posedge WB_CLK_I);
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repeat(Delay) @(posedge WB_CLK_I);
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wait (~WishboneBusy);
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wait (~WishboneBusy);
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WishboneBusy = 1;
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WishboneBusy = 1;
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#1;
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#1;
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WB_ADR_I = {20'h20, rr[11:0]};
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// WB_ADR_I = {20'h20, rr[11:0]};
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WB_ADR_I = {22'h02, rr[9:0]};
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$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
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$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
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WB_WE_I = 1'b1;
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WB_WE_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_STB_I = 1'b1;
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WB_STB_I = 1'b1;
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