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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/07/19 13:57:53 mohor
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// Testing environment also includes traffic cop, memory interface and host
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// interface.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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| Line 222... |
Line 226... |
begin
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begin
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wb_clk_o=0;
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wb_clk_o=0;
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// forever #2.5 wb_clk_o = ~wb_clk_o; // 2*2.5 ns -> 200.0 MHz
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// forever #2.5 wb_clk_o = ~wb_clk_o; // 2*2.5 ns -> 200.0 MHz
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// forever #5 wb_clk_o = ~wb_clk_o; // 2*5 ns -> 100.0 MHz
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// forever #5 wb_clk_o = ~wb_clk_o; // 2*5 ns -> 100.0 MHz
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// forever #10 wb_clk_o = ~wb_clk_o; // 2*10 ns -> 50.0 MHz
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// forever #10 wb_clk_o = ~wb_clk_o; // 2*10 ns -> 50.0 MHz
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// forever #12.5 wb_clk_o = ~wb_clk_o; // 2*12.5 ns -> 40 MHz
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forever #12.5 wb_clk_o = ~wb_clk_o; // 2*12.5 ns -> 40 MHz
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// forever #15 wb_clk_o = ~wb_clk_o; // 2*10 ns -> 33.3 MHz
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// forever #15 wb_clk_o = ~wb_clk_o; // 2*10 ns -> 33.3 MHz
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forever #20 wb_clk_o = ~wb_clk_o; // 2*20 ns -> 25 MHz
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// forever #20 wb_clk_o = ~wb_clk_o; // 2*20 ns -> 25 MHz
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// forever #25 wb_clk_o = ~wb_clk_o; // 2*25 ns -> 20.0 MHz
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// forever #25 wb_clk_o = ~wb_clk_o; // 2*25 ns -> 20.0 MHz
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// forever #31.25 wb_clk_o = ~wb_clk_o; // 2*31.25 ns -> 16.0 MHz
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// forever #31.25 wb_clk_o = ~wb_clk_o; // 2*31.25 ns -> 16.0 MHz
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// forever #50 wb_clk_o = ~wb_clk_o; // 2*50 ns -> 10.0 MHz
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// forever #50 wb_clk_o = ~wb_clk_o; // 2*50 ns -> 10.0 MHz
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// forever #55 wb_clk_o = ~wb_clk_o; // 2*55 ns -> 9.1 MHz
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// forever #55 wb_clk_o = ~wb_clk_o; // 2*55 ns -> 9.1 MHz
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end
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end
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Line 247... |
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// Generating mrx_clk clock
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// Generating mrx_clk clock
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initial
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initial
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begin
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begin
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mrx_clk=0;
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mrx_clk=0;
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#16 forever #20 mrx_clk = ~mrx_clk; // 2*20 ns -> 25 MHz
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// #16 forever #20 mrx_clk = ~mrx_clk; // 2*20 ns -> 25 MHz
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// #16 forever #200 mrx_clk = ~mrx_clk; // 2*200 ns -> 2.5 MHz
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#16 forever #200 mrx_clk = ~mrx_clk; // 2*200 ns -> 2.5 MHz
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end
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end
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reg [31:0] tmp;
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reg [31:0] tmp;
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initial
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initial
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begin
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begin
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