| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/09/06 11:03:24 mohor
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// Valid testbench.
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//
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// Revision 1.3 2002/07/23 16:34:31 mohor
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// Revision 1.3 2002/07/23 16:34:31 mohor
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// gsr added for use when ETH_XILINX_RAMB4 define is set.
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// gsr added for use when ETH_XILINX_RAMB4 define is set.
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//
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//
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// Revision 1.2 2002/07/19 14:02:47 mohor
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// Revision 1.2 2002/07/19 14:02:47 mohor
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// Clock mrx_clk set to 2.5 MHz.
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// Clock mrx_clk set to 2.5 MHz.
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| Line 309... |
Line 312... |
eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h4); // Enable Tx Flow control
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eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h4); // Enable Tx Flow control
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eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h5); // Enable Tx Flow control
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eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h5); // Enable Tx Flow control
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eth_host.wb_write(`ETH_TX_CTRL, 4'hf, 32'h10013); // Send Control frame with PAUSE_TV=0x0013
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eth_host.wb_write(`ETH_TX_CTRL, 4'hf, 32'h10013); // Send Control frame with PAUSE_TV=0x0013
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*/
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*/
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send_packet;
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send_packet;
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*/
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GetDataOnMRxD(100, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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GetDataOnMRxD(100, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
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repeat (1000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
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repeat (1000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
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