| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.8 2002/09/13 14:50:15 mohor
|
|
// Bug in MIIM fixed.
|
|
//
|
// Revision 1.7 2002/09/13 12:29:14 mohor
|
// Revision 1.7 2002/09/13 12:29:14 mohor
|
// Headers changed.
|
// Headers changed.
|
//
|
//
|
// Revision 1.6 2002/09/13 11:57:20 mohor
|
// Revision 1.6 2002/09/13 11:57:20 mohor
|
// New testbench. Thanks to Tadej M - "The Spammer".
|
// New testbench. Thanks to Tadej M - "The Spammer".
|
| Line 59... |
Line 62... |
//
|
//
|
//
|
//
|
//
|
//
|
|
|
|
|
`define TIME $display(" Time: %0t", $time)
|
|
|
|
`include "eth_phy_defines.v"
|
`include "eth_phy_defines.v"
|
`include "wb_model_defines.v"
|
`include "wb_model_defines.v"
|
`include "tb_eth_defines.v"
|
`include "tb_eth_defines.v"
|
`include "eth_defines.v"
|
`include "eth_defines.v"
|
`include "timescale.v"
|
`include "timescale.v"
|
| Line 386... |
Line 387... |
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
|
// Call tests
|
// Call tests
|
// ----------
|
// ----------
|
// test_access_to_mac_reg(0, 3); // 0 - 3
|
test_access_to_mac_reg(0, 3); // 0 - 3
|
// test_mii(0, 17); // 0 - 17
|
// test_mii(0, 17); // 0 - 17
|
test_mii(0, 1); // 0 - 17
|
test_mii(0, 1); // 0 - 17
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(0);
|
eth_phy.carrier_sense_real_delay(0);
|
test_mac_full_duplex_transmit(0, 3); // 0 - (3)
|
test_mac_full_duplex_transmit(0, 3); // 0 - (3)
|
| Line 432... |
Line 433... |
integer i;
|
integer i;
|
integer i1;
|
integer i1;
|
integer i2;
|
integer i2;
|
integer i3;
|
integer i3;
|
integer fail;
|
integer fail;
|
|
integer test_num;
|
reg [31:0] addr;
|
reg [31:0] addr;
|
reg [31:0] data;
|
reg [31:0] data;
|
reg [31:0] data_max;
|
reg [31:0] data_max;
|
begin
|
begin
|
// ACCESS TO MAC REGISTERS TEST
|
// ACCESS TO MAC REGISTERS TEST
|
test_heading("ACCESS TO MAC REGISTERS TEST");
|
test_heading("ACCESS TO MAC REGISTERS TEST");
|
$display(" ");
|
$display(" ");
|
$display("ACCESS TO MAC REGISTERS TEST");
|
$display("ACCESS TO MAC REGISTERS TEST");
|
fail = 0;
|
fail = 0;
|
|
|
/* Register space
|
|
--------------
|
|
`define ETH_MODER `ETH_BASE + 32'h00 Mode Register
|
|
`define ETH_INT `ETH_BASE + 32'h04 Interrupt Source Register
|
|
`define ETH_INT_MASK `ETH_BASE + 32'h08 Interrupt Mask Register
|
|
`define ETH_IPGT `ETH_BASE + 32'h0C Back to Bak Inter Packet Gap Register
|
|
`define ETH_IPGR1 `ETH_BASE + 32'h10 Non Back to Back Inter Packet Gap Register 1
|
|
`define ETH_IPGR2 `ETH_BASE + 32'h14 Non Back to Back Inter Packet Gap Register 2
|
|
`define ETH_PACKETLEN `ETH_BASE + 32'h18 Packet Length Register (min. and max.)
|
|
`define ETH_COLLCONF `ETH_BASE + 32'h1C Collision and Retry Configuration Register
|
|
`define ETH_TX_BD_NUM `ETH_BASE + 32'h20 Transmit Buffer Descriptor Number Register
|
|
`define ETH_CTRLMODER `ETH_BASE + 32'h24 Control Module Mode Register
|
|
`define ETH_MIIMODER `ETH_BASE + 32'h28 MII Mode Register
|
|
`define ETH_MIICOMMAND `ETH_BASE + 32'h2C MII Command Register
|
|
`define ETH_MIIADDRESS `ETH_BASE + 32'h30 MII Address Register
|
|
`define ETH_MIITX_DATA `ETH_BASE + 32'h34 MII Transmit Data Register
|
|
`define ETH_MIIRX_DATA `ETH_BASE + 32'h38 MII Receive Data Register
|
|
`define ETH_MIISTATUS `ETH_BASE + 32'h3C MII Status Register
|
|
`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 MAC Individual Address Register 0
|
|
`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 MAC Individual Address Register 1
|
|
`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 Hash Register 0
|
|
`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C Hash Register 1
|
|
*/
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// test_access_to_mac_reg: ////
|
|
//// ////
|
|
//// 0: Walking 1 with single cycles across MAC regs. ////
|
|
//// 1: Walking 1 with single cycles across MAC buffer descript. ////
|
|
//// 2: Test max reg. values and reg. values after writing ////
|
|
//// inverse reset values and hard reset of the MAC ////
|
|
//// 3: Test buffer desc. RAM preserving values after hard reset ////
|
|
//// of the MAC and resetting the logic ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
begin
|
|
|
if ((start_task <= 0) && (end_task >= 0))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Walking 1 with single cycles across MAC regs. ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
|
begin
|
begin
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
| Line 624... |
Line 622... |
bit_end_1 = 31;
|
bit_end_1 = 31;
|
bit_start_2 = 32; // not used
|
bit_start_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
end
|
end
|
endcase
|
endcase
|
|
|
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
|
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
|
begin
|
begin
|
data = 1'b1 << i_data;
|
data = 1'b1 << i_data;
|
if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
|
if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
|
begin
|
;
|
end
|
|
else
|
else
|
begin
|
begin
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
| Line 661... |
Line 659... |
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0; // Errors were reported previously
|
fail = 0; // Errors were reported previously
|
end
|
end
|
|
|
|
|
if ((start_task <= 4) && (end_task >= 4)) // not used, since burst access to reg. is not supported
|
|
begin
|
|
/* // TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
|
test_name = "TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
|
`TIME; $display(" TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
|
data = 0;
|
|
burst_data = 0;
|
|
burst_tmp_data = 0;
|
|
i_length = 10; // two bursts for length 20
|
|
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
|
|
begin
|
|
for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
|
|
begin
|
|
wbm_init_waits = i;
|
|
wbm_subseq_waits = i1;
|
|
#1;
|
|
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
|
|
begin
|
|
data = 1'b1 << i_data;
|
|
#1;
|
|
for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
|
|
begin
|
|
burst_data = burst_data << 32;
|
|
// DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
|
|
if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
|
|
begin
|
|
#1 burst_data[31:0] = 0;
|
|
end
|
|
else
|
|
begin
|
|
#1 burst_data[31:0] = data;
|
|
end
|
|
end
|
|
#1;
|
|
// 2 burst writes
|
|
addr = `ETH_BASE; // address of a first burst
|
|
wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
|
|
burst_tmp_data = burst_data >> (32 * i_length);
|
|
addr = addr + 32'h28; // address of a second burst
|
|
wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
|
|
#1;
|
|
// 2 burst reads
|
|
addr = `ETH_BASE; // address of a first burst
|
|
wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
|
|
wbm_init_waits, wbm_subseq_waits); // first burst
|
|
burst_tmp_data = burst_tmp_data << (32 * i_length);
|
|
addr = addr + 32'h28; // address of a second burst
|
|
wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
|
|
wbm_init_waits, wbm_subseq_waits); // second burst
|
|
#1;
|
|
for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
|
|
begin
|
|
// set ranges of R/W bits
|
|
case (`ETH_BASE + i2)
|
|
`ETH_MODER:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 16;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_INT: // READONLY - tested within INT test
|
|
begin
|
|
bit_start_1 = 32; // not used
|
|
bit_end_1 = 32; // not used
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_INT_MASK:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 6;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_IPGT:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 6;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_IPGR1:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 6;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_IPGR2:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 6;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_PACKETLEN:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 31;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_COLLCONF:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 5;
|
|
bit_start_2 = 16;
|
|
bit_end_2 = 19;
|
|
end
|
|
`ETH_TX_BD_NUM:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 7;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_CTRLMODER:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 2;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIIMODER:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 9;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
|
|
begin
|
|
bit_start_1 = 32; // not used
|
|
bit_end_1 = 32; // not used
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIIADDRESS:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 4;
|
|
bit_start_2 = 8;
|
|
bit_end_2 = 12;
|
|
end
|
|
`ETH_MIITX_DATA:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 15;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIIRX_DATA: // READONLY - tested within MIIM test
|
|
begin
|
|
bit_start_1 = 32; // not used
|
|
bit_end_1 = 32; // not used
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIISTATUS: // READONLY - tested within MIIM test
|
|
begin
|
|
bit_start_1 = 32; // not used
|
|
bit_end_1 = 32; // not used
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MAC_ADDR0:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 31;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MAC_ADDR1:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 15;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_HASH_ADDR0:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 31;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
default: // `ETH_HASH_ADDR1:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 31;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
endcase
|
|
#1;
|
|
// 3 LSBits of MIICOMMAND are NOT written !!!
|
|
if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
|
|
begin
|
|
if (burst_tmp_data[31:0] !== burst_data[31:0])
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
|
|
`TIME;
|
|
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
|
|
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
|
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
|
|
begin
|
|
if (burst_tmp_data[31:0] !== burst_data[31:0])
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail("RW bit of the MAC register was not written or not read");
|
|
`TIME;
|
|
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
|
|
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
|
|
end
|
|
end
|
|
else // data should not be equal to tmp_data
|
|
begin
|
|
if (burst_tmp_data[31:0] === burst_data[31:0])
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
|
|
`TIME;
|
|
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
|
|
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
|
|
end
|
|
end
|
|
end
|
|
burst_tmp_data = burst_tmp_data >> 32;
|
|
burst_data = burst_data >> 32;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;*/
|
|
end
|
|
|
|
|
|
if ((start_task <= 1) && (end_task >= 1))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Walking 1 with single cycles across MAC buffer descript. ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
|
begin
|
begin
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
// TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
test_name = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
|
|
| Line 978... |
Line 735... |
|
|
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
|
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
|
begin
|
begin
|
data = 1'b1 << i_data;
|
data = 1'b1 << i_data;
|
if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
|
if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
|
begin
|
;
|
end
|
|
else
|
else
|
begin
|
begin
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
| Line 1010... |
Line 766... |
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
// INTERMEDIATE DISPLAYS
|
case (i)
|
case (i)
|
0: $display(" buffer descriptors tested with 0 bus delay");
|
0: $display(" buffer descriptors tested with 0 bus delay");
|
1: $display(" buffer descriptors tested with 1 bus delay cycle");
|
1: $display(" buffer descriptors tested with 1 bus delay cycle");
|
2: $display(" buffer descriptors tested with 2 bus delay cycles");
|
2: $display(" buffer descriptors tested with 2 bus delay cycles");
|
3: $display(" buffer descriptors tested with 3 bus delay cycles");
|
3: $display(" buffer descriptors tested with 3 bus delay cycles");
|
| Line 1024... |
Line 781... |
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
/* Register RESET values MAX. values
|
|
-----------------------------------------
|
|
ETH_MODER 32'h0000_A800 32'h0000_A800 Mode Register
|
|
ETH_INT 32'h0000_0000 32'h0000_0000 Interrupt Source Register
|
|
ETH_INT_MASK 32'h0000_0000 32'h0000_0000 Interrupt Mask Register
|
|
ETH_IPGT 32'h0000_0012 32'h0000_0012 Back to Bak Inter Packet Gap Register
|
|
ETH_IPGR1 32'h0000_000C 32'h0000_000C Non Back to Back Inter Packet Gap Register 1
|
|
ETH_IPGR2 32'h0000_0012 32'h0000_0012 Non Back to Back Inter Packet Gap Register 2
|
|
ETH_PACKETLEN 32'h0040_0600 32'h0040_0600 Packet Length Register (min. and max.)
|
|
ETH_COLLCONF 32'h000F_003F 32'h000F_003F Collision and Retry Configuration Register
|
|
ETH_TX_BD_NUM 32'h0000_0040 32'h0000_0080 Transmit Buffer Descriptor Number Register
|
|
ETH_CTRLMODER 32'h0000_0000 32'h0000_0000 Control Module Mode Register
|
|
ETH_MIIMODER 32'h0000_0064 32'h0000_0064 MII Mode Register
|
|
ETH_MIICOMMAND 32'h0000_0000 32'h0000_0000 MII Command Register
|
|
ETH_MIIADDRESS 32'h0000_0000 32'h0000_0000 MII Address Register
|
|
ETH_MIITX_DATA 32'h0000_0000 32'h0000_0000 MII Transmit Data Register
|
|
ETH_MIIRX_DATA 32'h0000_0000 32'h0000_0000 MII Receive Data Register
|
|
ETH_MIISTATUS 32'h0000_0000 32'h0000_0000 MII Status Register
|
|
ETH_MAC_ADDR0 32'h0000_0000 32'h0000_0000 MAC Individual Address Register 0
|
|
ETH_MAC_ADDR1 32'h0000_0000 32'h0000_0000 MAC Individual Address Register 1
|
|
ETH_HASH_ADDR0 32'h0000_0000 32'h0000_0000 Hash Register 0
|
|
ETH_HASH_ADDR1 32'h0000_0000 32'h0000_0000 Hash Register 1
|
|
*/
|
|
|
|
|
|
if ((start_task <= 2) && (end_task >= 2))
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test max reg. values and reg. values after writing ////
|
|
//// inverse reset values and hard reset of the MAC ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 2) // Start this task
|
begin
|
begin
|
// TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
// TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
test_name =
|
test_name =
|
"TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
"TEST MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
`TIME; $display(
|
`TIME; $display(
|
| Line 1242... |
Line 981... |
end
|
end
|
end
|
end
|
end
|
end
|
// reset MAC registers
|
// reset MAC registers
|
if ((i == 0) || (i == 3))
|
if ((i == 0) || (i == 3))
|
begin
|
|
hard_reset;
|
hard_reset;
|
end
|
end
|
end
|
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if ((start_task <= 3) && (end_task >= 3))
|
if (test_num == 3) // Start this task
|
begin
|
begin
|
// TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
// TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
test_name = "TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
test_name = "TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
`TIME;
|
`TIME;
|
$display(" TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
$display(" TEST BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
| Line 1311... |
Line 1048... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
|
if (test_num == 4) // Start this task
|
|
begin
|
|
/* // TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
|
test_name = "TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
|
`TIME; $display(" TEST 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
|
data = 0;
|
|
burst_data = 0;
|
|
burst_tmp_data = 0;
|
|
i_length = 10; // two bursts for length 20
|
|
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
|
|
begin
|
|
for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
|
|
begin
|
|
wbm_init_waits = i;
|
|
wbm_subseq_waits = i1;
|
|
#1;
|
|
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
|
|
begin
|
|
data = 1'b1 << i_data;
|
|
#1;
|
|
for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
|
|
begin
|
|
burst_data = burst_data << 32;
|
|
// DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
|
|
if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
|
|
begin
|
|
#1 burst_data[31:0] = 0;
|
|
end
|
|
else
|
|
begin
|
|
#1 burst_data[31:0] = data;
|
|
end
|
|
end
|
|
#1;
|
|
// 2 burst writes
|
|
addr = `ETH_BASE; // address of a first burst
|
|
wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
|
|
burst_tmp_data = burst_data >> (32 * i_length);
|
|
addr = addr + 32'h28; // address of a second burst
|
|
wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
|
|
#1;
|
|
// 2 burst reads
|
|
addr = `ETH_BASE; // address of a first burst
|
|
wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
|
|
wbm_init_waits, wbm_subseq_waits); // first burst
|
|
burst_tmp_data = burst_tmp_data << (32 * i_length);
|
|
addr = addr + 32'h28; // address of a second burst
|
|
wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
|
|
wbm_init_waits, wbm_subseq_waits); // second burst
|
|
#1;
|
|
for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
|
|
begin
|
|
// set ranges of R/W bits
|
|
case (`ETH_BASE + i2)
|
|
`ETH_MODER:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 16;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_INT: // READONLY - tested within INT test
|
|
begin
|
|
bit_start_1 = 32; // not used
|
|
bit_end_1 = 32; // not used
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_INT_MASK:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 6;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_IPGT:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 6;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_IPGR1:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 6;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_IPGR2:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 6;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_PACKETLEN:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 31;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_COLLCONF:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 5;
|
|
bit_start_2 = 16;
|
|
bit_end_2 = 19;
|
|
end
|
|
`ETH_TX_BD_NUM:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 7;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_CTRLMODER:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 2;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIIMODER:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 9;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
|
|
begin
|
|
bit_start_1 = 32; // not used
|
|
bit_end_1 = 32; // not used
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIIADDRESS:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 4;
|
|
bit_start_2 = 8;
|
|
bit_end_2 = 12;
|
|
end
|
|
`ETH_MIITX_DATA:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 15;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIIRX_DATA: // READONLY - tested within MIIM test
|
|
begin
|
|
bit_start_1 = 32; // not used
|
|
bit_end_1 = 32; // not used
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MIISTATUS: // READONLY - tested within MIIM test
|
|
begin
|
|
bit_start_1 = 32; // not used
|
|
bit_end_1 = 32; // not used
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MAC_ADDR0:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 31;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_MAC_ADDR1:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 15;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
`ETH_HASH_ADDR0:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 31;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
default: // `ETH_HASH_ADDR1:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 31;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
|
endcase
|
|
#1;
|
|
// 3 LSBits of MIICOMMAND are NOT written !!!
|
|
if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
|
|
begin
|
|
if (burst_tmp_data[31:0] !== burst_data[31:0])
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
|
|
`TIME;
|
|
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
|
|
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
|
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
|
|
begin
|
|
if (burst_tmp_data[31:0] !== burst_data[31:0])
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail("RW bit of the MAC register was not written or not read");
|
|
`TIME;
|
|
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
|
|
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
|
|
end
|
|
end
|
|
else // data should not be equal to tmp_data
|
|
begin
|
|
if (burst_tmp_data[31:0] === burst_data[31:0])
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
|
|
`TIME;
|
|
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
|
|
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
|
|
end
|
|
end
|
|
end
|
|
burst_tmp_data = burst_tmp_data >> 32;
|
|
burst_data = burst_data >> 32;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;*/
|
|
end
|
|
|
|
end
|
|
|
end
|
end
|
endtask // test_access_to_mac_reg
|
endtask // test_access_to_mac_reg
|
|
|
|
|
task test_mii;
|
task test_mii;
|
