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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Diff between revs 243 and 252

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Line 40... Line 40...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.19  2002/11/14 13:12:47  tadejm
 
// Late collision is not reported any more.
 
//
// Revision 1.18  2002/10/18 17:03:34  tadejm
// Revision 1.18  2002/10/18 17:03:34  tadejm
// Changed BIST scan signals.
// Changed BIST scan signals.
//
//
// Revision 1.17  2002/10/18 13:58:22  tadejm
// Revision 1.17  2002/10/18 13:58:22  tadejm
// Some code changed due to bug fixes.
// Some code changed due to bug fixes.
Line 13212... Line 13215...
      else if (num_of_frames < 70)
      else if (num_of_frames < 70)
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
      else if (num_of_frames < 78)
      else if (num_of_frames < 78)
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
      // CHECK END OF RECEIVE
      // CHECK END OF RECEIVE
 
      // receive just preamble between some packets
 
      if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
 
      begin
 
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
 
        @(posedge mrx_clk);
 
        wait (MRxDV === 1'b0); // end receive
 
        repeat(10) @(posedge mrx_clk);
 
        repeat(15) @(posedge wb_clk);
 
      end
 
      // receiving frames and checking end of them
      frame_ended = 0;
      frame_ended = 0;
      check_frame = 0;
      check_frame = 0;
      fork
      fork
        begin
        begin
          if (i_length[0] == 1'b0)
          if (i_length[0] == 1'b0)
Line 13275... Line 13288...
          `TIME; $display("*E Wrong data of the received packet");
          `TIME; $display("*E Wrong data of the received packet");
          test_fail("Wrong data of the received packet");
          test_fail("Wrong data of the received packet");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
 
 
      // check WB INT signal
      // check WB INT signal
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
        begin
        begin
Line 13295... Line 13307...
          `TIME; $display("*E WB INT signal should not be set");
          `TIME; $display("*E WB INT signal should not be set");
          test_fail("WB INT signal should not be set");
          test_fail("WB INT signal should not be set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
 
 
      // check RX buffer descriptor of a packet
      // check RX buffer descriptor of a packet
      if (num_of_frames >= min_tmp)
      if (num_of_frames >= min_tmp)
      begin
      begin
        if ( (data[15:0] !== 16'h6000) && // wrap bit
        if ( (data[15:0] !== 16'h6000) && // wrap bit
             (data[15:0] !== 16'h4000) ) // without wrap bit
             (data[15:0] !== 16'h4000) ) // without wrap bit
Line 13388... Line 13399...
        fail = fail + 1;
        fail = fail + 1;
      end
      end
      // INTERMEDIATE DISPLAYS
      // INTERMEDIATE DISPLAYS
      if (num_of_frames == 3)
      if (num_of_frames == 3)
      begin
      begin
        $display("    pads appending to packets is selected");
 
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
                 0, 3);
                 0, 3);
      end
      end
      else if (num_of_frames == 9)
      else if (num_of_frames == 9)
Line 13517... Line 13527...
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
    speed = 100;
    speed = 100;
 
 
    frame_ended = 0;
    frame_ended = 0;
    num_of_frames = 0;
    num_of_frames = 0;// 0; // 10;
    num_of_bd = 120;
    num_of_bd = 120;
    i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
    i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
    while ((i_length + 4) < 78) // (min_tmp - 4))
    while ((i_length + 4) < 78) // (min_tmp - 4))
    begin
    begin
      // append CRC to packet
      // append CRC to packet
      if ((i_length[0] == 1'b0) && (i_length > 0))
      if ((i_length[0] == 1'b0) && (num_of_frames > 4))
        append_rx_crc (0, i_length, 1'b0, 1'b0);
        append_rx_crc (0, i_length, 1'b0, 1'b0);
      else if (i_length > 0)
      else if (num_of_frames > 4)
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
      // choose generating carrier sense and collision
      // choose generating carrier sense and collision
      case (i_length[1:0])
      case (i_length[1:0])
      2'h0:
      2'h0:
      begin
      begin
Line 13730... Line 13740...
      else if (num_of_frames < 70)
      else if (num_of_frames < 70)
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
      else if (num_of_frames < 78)
      else if (num_of_frames < 78)
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
      // CHECK END OF RECEIVE
      // CHECK END OF RECEIVE
 
      // receive just preamble between some packets
 
      if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
 
      begin
 
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
 
        @(posedge mrx_clk);
 
        wait (MRxDV === 1'b0); // end receive
 
        repeat(10) @(posedge mrx_clk);
 
        repeat(15) @(posedge wb_clk);
 
      end
 
      // receiving frames and checking end of them
      frame_ended = 0;
      frame_ended = 0;
      check_frame = 0;
      check_frame = 0;
      fork
      fork
        begin
        begin
          if (i_length[0] == 1'b0)
          if (i_length[0] == 1'b0)
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
          else
          else
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
          repeat(10) @(posedge mrx_clk);
          repeat(10) @(posedge mrx_clk);
        end
        end
        begin: fr_end2
        begin: fr_end1
          wait (MRxDV === 1'b1); // start receive
          wait (MRxDV === 1'b1); // start receive
          #1 check_rx_bd(num_of_bd, data);
          #1 check_rx_bd(num_of_bd, data);
          if (data[15] !== 1)
          if (data[15] !== 1)
          begin
          begin
            test_fail("Wrong buffer descriptor's empty bit read out from MAC");
            test_fail("Wrong buffer descriptor's empty bit read out from MAC");
Line 13767... Line 13787...
          repeat(15) @(posedge wb_clk);
          repeat(15) @(posedge wb_clk);
          check_frame = 1;
          check_frame = 1;
        end
        end
      join
      join
      // check length of a PACKET
      // check length of a PACKET
      if ( (data[31:16] != (i_length + 4))/* && (frame_ended == 1)*/ )
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
 
           ((data[31:16] != 0) && (num_of_frames < 3)) )
      begin
      begin
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
                        data[31:16], (i_length + 4));
                        data[31:16], (i_length + 4));
        test_fail("Wrong length of the packet out from PHY");
        test_fail("Wrong length of the packet out from PHY");
        fail = fail + 1;
        fail = fail + 1;
      end
      end
      // check received RX packet data and CRC
      // check received RX packet data and CRC
      if ((frame_ended == 1) && (num_of_frames >= 5))
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
      begin
      begin                                           // CRC has 4 bytes for itself
        if (i_length[0] == 1'b0)
        if (i_length[0] == 1'b0)
        begin
        begin
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
        end
        end
        else
        else
Line 13792... Line 13813...
          `TIME; $display("*E Wrong data of the received packet");
          `TIME; $display("*E Wrong data of the received packet");
          test_fail("Wrong data of the received packet");
          test_fail("Wrong data of the received packet");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
 
 
      // check WB INT signal
      // check WB INT signal
      if (num_of_frames >= 5)
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
      begin
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
        if (wb_int !== 1'b1)
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
        begin
        begin
          `TIME; $display("*E WB INT signal should be set");
          `TIME; $display("*E WB INT signal should be set");
          test_fail("WB INT signal should be set");
          test_fail("WB INT signal should be set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
Line 13812... Line 13832...
          `TIME; $display("*E WB INT signal should not be set");
          `TIME; $display("*E WB INT signal should not be set");
          test_fail("WB INT signal should not be set");
          test_fail("WB INT signal should not be set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
 
 
      // display RX buffer descriptor of a packet with length smaller than 7
 
      check_rx_bd(num_of_bd, data);
 
      if (num_of_frames <= 6)
 
      begin
 
        `TIME; $display("=> RX buffer descriptor is: %0h - len: %0d", data[15:0], num_of_frames);
 
      end
 
      // check RX buffer descriptor of a packet
      // check RX buffer descriptor of a packet
      if (num_of_frames >= min_tmp)
      if (num_of_frames >= min_tmp)
      begin
      begin
        if ( (data[15:0] !== 16'h6000) && // wrap bit
        if ( (data[15:0] !== 16'h6000) && // wrap bit
             (data[15:0] !== 16'h4000) ) // without wrap bit
             (data[15:0] !== 16'h4000) ) // without wrap bit
Line 13861... Line 13874...
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      // check interrupts
      // check interrupts
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      if (num_of_frames >= 40)
      if (num_of_frames >= 5)
      begin
      begin
        if ((data & `ETH_INT_RXB) !== 1'b1)//`ETH_INT_RXB)
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
        begin
        begin
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
          test_fail("Interrupt Receive Buffer was not set");
          test_fail("Interrupt Receive Buffer was not set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
Line 13876... Line 13889...
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
          test_fail("Other interrupts (except Receive Buffer) were set");
          test_fail("Other interrupts (except Receive Buffer) were set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
 
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
 
      begin
 
        if (data) // Checking if any interrupt is pending)
 
        begin
 
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
 
          test_fail("Interrupts were set");
 
          fail = fail + 1;
 
        end
 
      end
      else
      else
      begin
      begin
        if ((data & `ETH_INT_RXE) !== 1'b1)//`ETH_INT_RXE)
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
        begin
        begin
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
          test_fail("Interrupt Receive Buffer Error was not set");
          test_fail("Interrupt Receive Buffer Error was not set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
Line 13902... Line 13924...
        fail = fail + 1;
        fail = fail + 1;
      end
      end
      // INTERMEDIATE DISPLAYS
      // INTERMEDIATE DISPLAYS
      if (num_of_frames == 3)
      if (num_of_frames == 3)
      begin
      begin
        $display("    pads appending to packets is selected");
 
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
                 0, 3);
                 0, 3);
      end
      end
      else if (num_of_frames == 9)
      else if (num_of_frames == 9)

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