| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.31 2003/12/05 12:46:26 tadejm
|
|
// Updated testbench. Some more testcases, some repaired.
|
|
//
|
// Revision 1.30 2003/10/17 07:45:17 markom
|
// Revision 1.30 2003/10/17 07:45:17 markom
|
// mbist signals updated according to newest convention
|
// mbist signals updated according to newest convention
|
//
|
//
|
// Revision 1.29 2003/08/20 12:06:24 mohor
|
// Revision 1.29 2003/08/20 12:06:24 mohor
|
// Artisan RAMs added.
|
// Artisan RAMs added.
|
| Line 493... |
Line 496... |
|
|
// Call tests
|
// Call tests
|
// ----------
|
// ----------
|
test_access_to_mac_reg(0, 4); // 0 - 4
|
test_access_to_mac_reg(0, 4); // 0 - 4
|
test_mii(0, 17); // 0 - 17
|
test_mii(0, 17); // 0 - 17
|
|
$display("");
|
|
$display("===========================================================================");
|
|
$display("PHY generates ideal Carrier sense and Collision signals for following tests");
|
|
$display("===========================================================================");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(0);
|
eth_phy.carrier_sense_real_delay(0);
|
// test_mac_full_duplex_transmit(0, 21); // 0 - (21)
|
test_mac_full_duplex_transmit(0, 21); // 0 - 21
|
|
test_mac_full_duplex_receive(0, 13); // 0 - 13
|
|
test_mac_full_duplex_flow_control(0, 5); // 0 - 5
|
// test_mac_full_duplex_receive(2, 2); // 0 - 13
|
test_mac_half_duplex_flow(0, 1);
|
// test_mac_full_duplex_flow_control(0, 4); // 0 - 4
|
|
// 4 is executed, everything is OK
|
|
// test_mac_half_duplex_flow(0, 0);
|
|
|
|
|
$display("");
|
|
$display("===========================================================================");
|
|
$display("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
|
|
$display("===========================================================================");
|
test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
|
test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(1);
|
eth_phy.carrier_sense_real_delay(1);
|
|
test_mac_full_duplex_transmit(0, 21); // 0 - 21
|
|
test_mac_full_duplex_receive(0, 13); // 0 - 13
|
|
test_mac_full_duplex_flow_control(0, 5); // 0 - 5
|
|
test_mac_half_duplex_flow(0, 1);
|
|
|
|
|
// Finish test's logs
|
// Finish test's logs
|
test_summary;
|
test_summary;
|
$display("\n\n END of SIMULATION");
|
$display("\n\n END of SIMULATION");
|
| Line 580... |
Line 592... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Byte selects on 4 32-bit RW registers. ////
|
//// Byte selects on 4 32-bit RW registers. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
|
if (test_num == 0) //
|
begin
|
begin
|
// TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
|
// TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
| Line 667... |
Line 679... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Walking 1 with single cycles across MAC regs. ////
|
//// Walking 1 with single cycles across MAC regs. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) // Walking 1 with single cycles across MAC regs.
|
if (test_num == 1) //
|
begin
|
begin
|
// TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
// TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
| Line 896... |
Line 908... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Walking 1 with single cycles across MAC buffer descript. ////
|
//// Walking 1 with single cycles across MAC buffer descript. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) // Start Walking 1 with single cycles across MAC buffer descript.
|
if (test_num == 2) //
|
begin
|
begin
|
// TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
// TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
test_name = "TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
|
|
| Line 1024... |
Line 1036... |
//// ////
|
//// ////
|
//// Test max reg. values and reg. values after writing ////
|
//// Test max reg. values and reg. values after writing ////
|
//// inverse reset values and hard reset of the MAC ////
|
//// inverse reset values and hard reset of the MAC ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) // Start this task
|
if (test_num == 3) //
|
begin
|
begin
|
// TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
// TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
test_name =
|
test_name =
|
"TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
"TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
`TIME; $display(
|
`TIME; $display(
|
| Line 1247... |
Line 1259... |
//// ////
|
//// ////
|
//// Test buffer desc. ram preserving values after hard reset ////
|
//// Test buffer desc. ram preserving values after hard reset ////
|
//// of the mac and reseting the logic ////
|
//// of the mac and reseting the logic ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 4) // Start this task
|
if (test_num == 4) //
|
begin
|
begin
|
// TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
// TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
test_name = "TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
test_name = "TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
`TIME;
|
`TIME;
|
$display(" TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
$display(" TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
| Line 1299... |
Line 1311... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if (test_num == 5) // Start this task
|
if (test_num == 5) //
|
begin
|
begin
|
/* // TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
/* // TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
| Line 1627... |
Line 1639... |
//// ////
|
//// ////
|
//// Test clock divider of mii management module with all ////
|
//// Test clock divider of mii management module with all ////
|
//// possible frequences. ////
|
//// possible frequences. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
|
if (test_num == 0) //
|
begin
|
begin
|
// TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
|
// TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
|
test_name = "TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
|
test_name = "TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
|
`TIME; $display(" TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
|
`TIME; $display(" TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
|
|
|
| Line 1700... |
Line 1712... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test various readings from 'real' phy registers. ////
|
//// Test various readings from 'real' phy registers. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) // Test various readings from 'real' phy registers.
|
if (test_num == 1) //
|
begin
|
begin
|
// TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS
|
// TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS
|
test_name = "TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
|
test_name = "TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
|
`TIME; $display(" TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
|
`TIME; $display(" TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
|
|
|
| Line 2491... |
Line 2503... |
begin
|
begin
|
// TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
|
// TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
clk_div = 64;
|
clk_div = 64;
|
mii_set_clk_div(clk_div[7:0]);
|
mii_set_clk_div(clk_div[7:0]);
|
| Line 2689... |
Line 2700... |
begin
|
begin
|
// TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
|
// TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
clk_div = 64;
|
clk_div = 64;
|
mii_set_clk_div(clk_div[7:0]);
|
mii_set_clk_div(clk_div[7:0]);
|
| Line 2889... |
Line 2899... |
begin
|
begin
|
// TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
|
// TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set the MII
|
// set the MII
|
clk_div = 64;
|
clk_div = 64;
|
mii_set_clk_div(clk_div[7:0]);
|
mii_set_clk_div(clk_div[7:0]);
|
| Line 3137... |
Line 3146... |
begin
|
begin
|
// TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
// TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
|
test_name = "TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
test_name = "TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
|
`TIME; $display(" TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
`TIME; $display(" TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
|
|
|
reset_mii; // reset MII
|
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
// set link up, if it wasn't due to previous tests, since there weren't PHY registers
|
#Tp eth_phy.link_up_down(1);
|
#Tp eth_phy.link_up_down(1);
|
// set MII speed
|
// set MII speed
|
clk_div = 6;
|
clk_div = 6;
|
mii_set_clk_div(clk_div[7:0]);
|
mii_set_clk_div(clk_div[7:0]);
|
| Line 4269... |
Line 4277... |
$display("MAC FULL DUPLEX TRANSMIT TEST");
|
$display("MAC FULL DUPLEX TRANSMIT TEST");
|
fail = 0;
|
fail = 0;
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
//reset_mac;
|
|
//reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
/*
|
/*
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
| Line 4349... |
Line 4354... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test no transmit when all buffers are RX ( 10Mbps ). ////
|
//// Test no transmit when all buffers are RX ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) // Test no transmit when all buffers are RX ( 10Mbps ).
|
if (test_num == 0) //
|
begin
|
begin
|
// TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
|
// TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
|
test_name = "TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )";
|
test_name = "TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )";
|
`TIME; $display(" TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )");
|
`TIME; $display(" TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )");
|
|
|
| Line 4441... |
Line 4446... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test no transmit when all buffers are RX ( 100Mbps ). ////
|
//// Test no transmit when all buffers are RX ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) // Test no transmit when all buffers are RX ( 100Mbps ).
|
if (test_num == 1) //
|
begin
|
begin
|
// TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
|
// TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
|
test_name = "TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )";
|
test_name = "TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )";
|
`TIME; $display(" TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )");
|
`TIME; $display(" TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )");
|
|
|
| Line 4535... |
Line 4540... |
//// ////
|
//// ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// one TX buffer decriptor ( 10Mbps ). ////
|
//// one TX buffer decriptor ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) // without and with padding
|
if (test_num == 2) //
|
begin
|
begin
|
// TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
|
// TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
|
test_name = "TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
|
test_name = "TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
|
`TIME; $display(" TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
|
`TIME; $display(" TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
|
|
|
| Line 4849... |
Line 4854... |
//// ////
|
//// ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// one TX buffer decriptor ( 100Mbps ). ////
|
//// one TX buffer decriptor ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) // with and without padding
|
if (test_num == 3) //
|
begin
|
begin
|
// TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
|
// TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
|
test_name = "TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
|
test_name = "TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
|
`TIME; $display(" TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
|
`TIME; $display(" TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
|
|
|
| Line 5153... |
Line 5158... |
//// ////
|
//// ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// maximum TX buffer decriptors ( 10Mbps ). ////
|
//// maximum TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 4) // without and with padding
|
if (test_num == 4) //
|
begin
|
begin
|
// TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )
|
// TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )
|
test_name = "TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )";
|
test_name = "TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 5183... |
Line 5185... |
// prepare two packets of MAXFL length
|
// prepare two packets of MAXFL length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
st_data = 8'hA3;
|
st_data = 8'hA5;
|
set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
|
set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
|
st_data = 8'h81;
|
st_data = 8'h71;
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
| Line 5384... |
Line 5387... |
begin
|
begin
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
#1 check_tx_bd(num_of_bd, data);
|
#1 check_tx_bd(num_of_bd, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
| Line 5395... |
Line 5399... |
#1 check_tx_bd(num_of_bd, data);
|
#1 check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
|
repeat(2) @(posedge wb_clk);
|
|
repeat(2) @(posedge mrx_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
if (eth_phy.tx_len != (i_length + 4))
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC: %0d instead of %0d", eth_phy.tx_len, i_length + 4);
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// checking in the following if statement is performed only for first and last 64 lengths
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
if (i_length[0] == 0)
|
if (i_length[0] == 0)
|
begin
|
begin
|
check_tx_packet((`MEMORY_BASE + i_length[1:0]), 0, i_length, tmp);
|
check_tx_packet((`MEMORY_BASE + i_length[1:0]), 0, i_length, tmp);
|
end
|
end
|
| Line 5412... |
Line 5420... |
begin
|
begin
|
check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
|
check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
|
end
|
end
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
if (i_length[0] == 0)
|
if (i_length[0] == 0)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
else
|
else
|
check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check WB INT signal
|
// check WB INT signal
|
if (i_length[1:0] == 2'h0)
|
if (i_length[1:0] == 2'h0)
|
| Line 5505... |
Line 5515... |
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if ((i_length + 4) == (min_tmp + 7))
|
if ((i_length + 4) == (min_tmp + 7))
|
| Line 5613... |
Line 5624... |
//// ////
|
//// ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// maximum TX buffer decriptors ( 100Mbps ). ////
|
//// maximum TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 5) // with and without padding
|
if (test_num == 5) //
|
begin
|
begin
|
// TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )
|
// TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )
|
test_name = "TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )";
|
test_name = "TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 5650... |
Line 5658... |
st_data = 8'h71;
|
st_data = 8'h71;
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 100Mbps
|
| Line 5844... |
Line 5853... |
begin
|
begin
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
#1 check_tx_bd(num_of_bd, data);
|
#1 check_tx_bd(num_of_bd, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
| Line 5855... |
Line 5865... |
#1 check_tx_bd(num_of_bd, data);
|
#1 check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
|
repeat(2) @(posedge wb_clk);
|
|
repeat(2) @(posedge mrx_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
if (eth_phy.tx_len != (i_length + 4))
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC: %0d instead of %0d", eth_phy.tx_len, i_length + 4);
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// checking in the following if statement is performed only for first and last 64 lengths
|
// checking in the following if statement is performed only for first and last 64 lengths
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
| Line 5873... |
Line 5886... |
begin
|
begin
|
check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
|
check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
|
end
|
end
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
if (i_length[0] == 0)
|
if (i_length[0] == 0)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
else
|
else
|
check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check WB INT signal
|
// check WB INT signal
|
if (i_length[1:0] == 2'h0)
|
if (i_length[1:0] == 2'h0)
|
| Line 5966... |
Line 5981... |
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if ((i_length + 4) == (min_tmp + 7))
|
if ((i_length + 4) == (min_tmp + 7))
|
| Line 6082... |
Line 6098... |
test_name = "TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
|
test_name = "TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
|
`TIME; $display(" TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
|
`TIME; $display(" TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 6568... |
Line 6581... |
test_name = "TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
|
test_name = "TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
|
`TIME; $display(" TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
|
`TIME; $display(" TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 7053... |
Line 7063... |
test_name = "TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
|
test_name = "TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
|
`TIME; $display(" TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
|
`TIME; $display(" TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 7334... |
Line 7341... |
disable fr_st2;
|
disable fr_st2;
|
end
|
end
|
end
|
end
|
end
|
end
|
join
|
join
|
|
|
|
|
// check packets larger than 4 bytes
|
// check packets larger than 4 bytes
|
if (num_of_frames >= 5)
|
if (num_of_frames >= 5)
|
begin
|
begin
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
#1 check_tx_bd(num_of_bd, data);
|
#1 check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
|
|
|
|
// check length of a PACKET // Check this if it is OK igor
|
// check length of a PACKET // Check this if it is OK igor
|
if (num_of_frames < 6)
|
if (num_of_frames < 6)
|
begin
|
begin
|
if (eth_phy.tx_len != (i_length + 4))
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
| Line 7400... |
Line 7403... |
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
if (i_length[0] == 0)
|
if (i_length[0] == 0)
|
begin
|
begin
|
#1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
|
#1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
|
end
|
end
|
| Line 7417... |
Line 7419... |
begin
|
begin
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
|
end
|
end
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
#1;
|
#1;
|
| Line 7429... |
Line 7432... |
end
|
end
|
else
|
else
|
check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
|
check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check WB INT signal
|
// check WB INT signal
|
| Line 7454... |
Line 7458... |
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check TX buffer descriptor of a packet
|
// check TX buffer descriptor of a packet
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
|
|
if (num_of_frames >= 5)
|
if (num_of_frames >= 5)
|
begin
|
begin
|
if ((i_length[1] == 1'b0) && (i_length[0] == 1'b0)) // interrupt enabled
|
if ((i_length[1] == 1'b0) && (i_length[0] == 1'b0)) // interrupt enabled
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6000) && // wrap bit
|
if ( (data[15:0] !== 16'h6000) && // wrap bit
|
| Line 7553... |
Line 7556... |
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (i_length == 3)
|
if (i_length == 3)
|
| Line 7639... |
Line 7643... |
test_name = "TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
|
test_name = "TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
|
`TIME; $display(" TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
|
`TIME; $display(" TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
// set 8 TX buffer descriptors - must be set before TX enable
|
// set 8 TX buffer descriptors - must be set before TX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable TX, set full-duplex mode, padding and CRC appending
|
// enable TX, set full-duplex mode, padding and CRC appending
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
|
// wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare two packets of MAXFL length
|
// prepare two packets of MAXFL length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
| Line 7727... |
Line 7729... |
// detect carrier sense in FD and set collision
|
// detect carrier sense in FD and set collision
|
eth_phy.carrier_sense_tx_fd_detect(1);
|
eth_phy.carrier_sense_tx_fd_detect(1);
|
eth_phy.collision(1);
|
eth_phy.collision(1);
|
end
|
end
|
endcase
|
endcase
|
|
// // append CRC
|
|
// if ((i_length[0] == 1'b0) && (num_of_frames >= 6))
|
|
// begin
|
|
// append_tx_crc(`MEMORY_BASE, i_length, 1'b0);
|
|
// end
|
#1;
|
#1;
|
// first destination address on ethernet PHY
|
// first destination address on ethernet PHY
|
eth_phy.set_tx_mem_addr(num_of_frames * 16);
|
eth_phy.set_tx_mem_addr(num_of_frames * 16);
|
// SET packets and wrap bit
|
// SET packets and wrap bit
|
// num_of_frames <= 9 => wrap set to TX BD 0
|
// num_of_frames <= 9 => wrap set to TX BD 0
|
if (num_of_frames <= 9)
|
if (num_of_frames <= 5)
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
|
if (tmp_len[0] == 0) // CRC appended by 'HARDWARE'
|
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
|
// set wrap bit
|
|
set_tx_bd_wrap(0);
|
|
end
|
|
else if (num_of_frames <= 9)
|
|
begin
|
|
tmp_len = i_length; // length of frame
|
|
tmp_bd_num = 0; // TX BD number
|
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
|
if (tmp_len[0] == 0) // CRC appended by 'SOFTWARE'
|
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
|
else
|
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
// set wrap bit
|
// set wrap bit
|
set_tx_bd_wrap(0);
|
set_tx_bd_wrap(0);
|
end
|
end
|
// 10 <= num_of_frames < 18 => wrap set to TX BD 3
|
// 10 <= num_of_frames < 18 => wrap set to TX BD 3
|
else if ((num_of_frames == 10) || (num_of_frames == 14))
|
else if ((num_of_frames == 10) || (num_of_frames == 14))
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 4) //
|
while (tmp_bd_num < 4)
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
| Line 7775... |
Line 7796... |
while (tmp_bd_num < 5) //
|
while (tmp_bd_num < 5) //
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else // when (num_of_frames == 23), (i_length == 23) and therefor i_length[0] == 1 !!!
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1],
|
|
((num_of_frames == 23) && (tmp_bd_num == 0)), 1'b1, (`MEMORY_BASE + max_tmp));
|
|
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
| Line 7795... |
Line 7818... |
while (tmp_bd_num < 6) //
|
while (tmp_bd_num < 6) //
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
| Line 7815... |
Line 7838... |
while (tmp_bd_num < 7) //
|
while (tmp_bd_num < 7) //
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
| Line 7835... |
Line 7858... |
while (tmp_bd_num < 8) //
|
while (tmp_bd_num < 8) //
|
begin
|
begin
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
|
else
|
else
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set TX BD number
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
| Line 7880... |
Line 7903... |
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
frame_started = 1;
|
frame_started = 1;
|
end
|
end
|
begin
|
begin
|
repeat (50) @(posedge mtx_clk);
|
repeat (50) @(posedge mtx_clk);
|
$display("(%0t) num_of_frames = 0x%0x", $time, num_of_frames);
|
|
if (num_of_frames < 5)
|
if (num_of_frames < 5)
|
begin
|
begin
|
if (frame_started == 1)
|
if (frame_started == 1)
|
begin
|
begin
|
`TIME; $display("*E Frame should NOT start!");
|
`TIME; $display("*E Frame should NOT start!");
|
| Line 7894... |
Line 7916... |
else
|
else
|
begin
|
begin
|
if (frame_started == 0)
|
if (frame_started == 0)
|
begin
|
begin
|
`TIME; $display("*W Frame should start!");
|
`TIME; $display("*W Frame should start!");
|
#500 $stop;
|
|
disable fr_st3;
|
disable fr_st3;
|
end
|
end
|
end
|
end
|
end
|
end
|
join
|
join
|
| Line 7910... |
Line 7931... |
begin
|
begin
|
#1 check_tx_bd(num_of_bd, data);
|
#1 check_tx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// check length of a PACKET
|
// check length of a PACKET // Check this if it is OK igor
|
if ((num_of_frames + 4) < 64)
|
if (num_of_frames < 6)
|
|
begin
|
|
if (eth_phy.tx_len != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames != 23) // 6 - 53 except 23
|
|
begin
|
|
if (i_length[0] == 1'b0)
|
|
begin
|
|
if (eth_phy.tx_len != i_length)
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (eth_phy.tx_len != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
end
|
|
else // num_of_frames == 23
|
|
begin
|
|
if (data[12]) // Padding
|
begin
|
begin
|
if (eth_phy.tx_len != 64)
|
if (eth_phy.tx_len != (64))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 7929... |
Line 7982... |
`TIME; $display("*E Wrong length of the packet out from MAC");
|
`TIME; $display("*E Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
|
end
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
if (i_length[0] == 0)
|
if (i_length[0] == 0)
|
begin
|
begin
|
#1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
|
#1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
|
end
|
end
|
|
else if (num_of_frames == 23) // i_length[0] == 1 here
|
|
begin
|
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
|
|
#1 check_tx_packet( 0, (num_of_frames * 16 + i_length), (min_tmp - i_length - 4), tmp);
|
|
end
|
else
|
else
|
begin
|
begin
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
|
#1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
|
end
|
end
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
#1 check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
|
#1;
|
|
if ((i_length[0] == 1'b0) && (num_of_frames >= 6))
|
|
begin
|
|
end
|
|
else
|
|
check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check WB INT signal
|
// check WB INT signal
|
| Line 7974... |
Line 8040... |
end
|
end
|
// check TX buffer descriptor of a packet
|
// check TX buffer descriptor of a packet
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
if (num_of_frames >= 5)
|
if (num_of_frames >= 5)
|
begin
|
begin
|
if (i_length[1] == 1'b0) // interrupt enabled
|
if ((i_length[1] == 1'b0) && (i_length[0] == 1'b0)) // interrupt enabled
|
begin
|
begin
|
if ( (data[15:0] !== 16'h7800) && // wrap bit
|
if ( (data[15:0] !== 16'h6000) && // wrap bit
|
(data[15:0] !== 16'h5800) ) // without wrap bit
|
(data[15:0] !== 16'h4000) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct 1: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else // interrupt not enabled
|
else if ((i_length[1] == 1'b1) && (i_length[0] == 1'b0)) // interrupt not enabled
|
|
begin
|
|
if ( (data[15:0] !== 16'h2000) && // wrap bit
|
|
(data[15:0] !== 16'h0000) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E TX buffer descriptor status is not correct 2: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if ((i_length[1] == 1'b0) && (i_length[0] == 1'b1)) // interrupt enabled
|
|
begin
|
|
if ( (data[15:0] !== 16'h6800) && // wrap bit
|
|
(data[15:0] !== 16'h4800) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E TX buffer descriptor status is not correct 3: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames != 23) // ((i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
|
|
begin
|
|
if ( (data[15:0] !== 16'h2800) && // wrap bit
|
|
(data[15:0] !== 16'h0800) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E TX buffer descriptor status is not correct 4: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else // ((num_of_frames != 23) && (i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
|
begin
|
begin
|
if ( (data[15:0] !== 16'h3800) && // wrap bit
|
if ( (data[15:0] !== 16'h3800) && // wrap bit
|
(data[15:0] !== 16'h1800) ) // without wrap bit
|
(data[15:0] !== 16'h1800) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct 5: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 8040... |
Line 8136... |
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (i_length == 3)
|
if (i_length == 3)
|
begin
|
begin
|
$display(" pads appending to packets is selected");
|
$display(" pads appending to packets is not selected (except for 0x23)");
|
$display(" using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
|
$display(" using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
|
$display(" ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
|
$display(" ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
|
0, 3);
|
0, 3);
|
end
|
end
|
else if (i_length == 9)
|
else if (i_length == 9)
|
| Line 8118... |
Line 8215... |
//// ////
|
//// ////
|
//// Test transmit packets across MAXFL value at ////
|
//// Test transmit packets across MAXFL value at ////
|
//// 13 TX buffer decriptors ( 10Mbps ). ////
|
//// 13 TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 10) // without and with padding
|
if (test_num == 10) //
|
begin
|
begin
|
// TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )
|
// TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )
|
test_name = "TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
|
test_name = "TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
|
|
|
| Line 8339... |
Line 8436... |
//// ////
|
//// ////
|
//// Test transmit packets across MAXFL value at ////
|
//// Test transmit packets across MAXFL value at ////
|
//// 13 TX buffer decriptors ( 100Mbps ). ////
|
//// 13 TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 11) // without and with padding
|
if (test_num == 11) //
|
begin
|
begin
|
// TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )
|
// TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )
|
test_name = "TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
|
test_name = "TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
|
|
|
| Line 8563... |
Line 8660... |
//// ////
|
//// ////
|
//// Test transmit packets across changed MAXFL value at ////
|
//// Test transmit packets across changed MAXFL value at ////
|
//// 47 TX buffer decriptors ( 10Mbps ). ////
|
//// 47 TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 12) // without and with padding
|
if (test_num == 12) //
|
begin
|
begin
|
// TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )
|
// TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )
|
test_name = "TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
|
test_name = "TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
|
|
|
| Line 8764... |
Line 8861... |
//// ////
|
//// ////
|
//// Test transmit packets across changed MAXFL value at ////
|
//// Test transmit packets across changed MAXFL value at ////
|
//// 47 TX buffer decriptors ( 100Mbps ). ////
|
//// 47 TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 13) // without and with padding
|
if (test_num == 13) //
|
begin
|
begin
|
// TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )
|
// TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )
|
test_name = "TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
|
test_name = "TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
|
|
|
| Line 8965... |
Line 9062... |
//// ////
|
//// ////
|
//// Test transmit packets across changed MINFL value at ////
|
//// Test transmit packets across changed MINFL value at ////
|
//// 7 TX buffer decriptors ( 10Mbps ). ////
|
//// 7 TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 14) // without and with padding
|
if (test_num == 14) //
|
begin
|
begin
|
// TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )
|
// TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )
|
test_name = "TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )";
|
test_name = "TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )");
|
|
|
| Line 9162... |
Line 9259... |
//// ////
|
//// ////
|
//// Test transmit packets across changed MINFL value at ////
|
//// Test transmit packets across changed MINFL value at ////
|
//// 7 TX buffer decriptors ( 100Mbps ). ////
|
//// 7 TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 15) // without and with padding
|
if (test_num == 15) //
|
begin
|
begin
|
// TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
|
// TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
|
test_name = "TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )";
|
test_name = "TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )");
|
|
|
| Line 9357... |
Line 9454... |
//// ////
|
//// ////
|
//// Test transmit packets across MAXFL with HUGEN at ////
|
//// Test transmit packets across MAXFL with HUGEN at ////
|
//// 19 TX buffer decriptors ( 10Mbps ). ////
|
//// 19 TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 16) // without and with padding
|
if (test_num == 16) //
|
begin
|
begin
|
// TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )
|
// TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )
|
test_name = "TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )";
|
test_name = "TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 9543... |
Line 9637... |
//// ////
|
//// ////
|
//// Test transmit packets across MAXFL with HUGEN at ////
|
//// Test transmit packets across MAXFL with HUGEN at ////
|
//// 19 TX buffer decriptors ( 100Mbps ). ////
|
//// 19 TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 17) // without and with padding
|
if (test_num == 17) //
|
begin
|
begin
|
// TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )
|
// TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )
|
test_name = "TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )";
|
test_name = "TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 9729... |
Line 9820... |
//// ////
|
//// ////
|
//// Test IPG during Back-to-Back transmit at ////
|
//// Test IPG during Back-to-Back transmit at ////
|
//// 88 TX buffer decriptors ( 10Mbps ). ////
|
//// 88 TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 18) // without and with padding
|
if (test_num == 18) //
|
begin
|
begin
|
// TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )
|
// TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )
|
test_name = "TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )";
|
test_name = "TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 9970... |
Line 10058... |
//// ////
|
//// ////
|
//// Test IPG during Back-to-Back transmit at ////
|
//// Test IPG during Back-to-Back transmit at ////
|
//// 88 TX buffer decriptors ( 100Mbps ). ////
|
//// 88 TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 19) // without and with padding
|
if (test_num == 19) //
|
begin
|
begin
|
// TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )
|
// TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )
|
test_name = "TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )";
|
test_name = "TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
| Line 10211... |
Line 10296... |
//// ////
|
//// ////
|
//// Test transmit packets after TX under-run on each packet's ////
|
//// Test transmit packets after TX under-run on each packet's ////
|
//// byte at 2 TX buffer decriptors ( 10Mbps ). ////
|
//// byte at 2 TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 20) // without padding
|
if (test_num == 20) //
|
begin
|
begin
|
// TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )
|
// TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )
|
test_name = "TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )";
|
test_name = "TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )";
|
`TIME;
|
`TIME;
|
$display(" TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )");
|
$display(" TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )");
|
| Line 10316... |
Line 10401... |
else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
|
else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
|
begin
|
begin
|
disable wait_fr;
|
disable wait_fr;
|
if (frame_ended == 1)
|
if (frame_ended == 1)
|
begin
|
begin
|
$display("(%0t) no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
|
$display(" ->no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
|
$time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
|
({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
|
no_underrun = 1;
|
no_underrun = 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wait (frame_ended == 1);
|
wait (frame_ended == 1);
|
$display("(%0t) under-run on %0d. byte",
|
$display(" ->under-run on %0d. byte",
|
$time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
|
({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
|
no_underrun = 0;
|
no_underrun = 0;
|
end
|
end
|
end
|
end
|
repeat (2) @(posedge wb_clk);
|
repeat (2) @(posedge wb_clk);
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
| Line 10364... |
Line 10449... |
// WAIT FOR FIRST TRANSMIT
|
// WAIT FOR FIRST TRANSMIT
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
wait (MTxEn === 1'b1); // start first transmit
|
wait (MTxEn === 1'b1); // start first transmit
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end first transmit
|
wait (MTxEn === 1'b0); // end first transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
| Line 10670... |
Line 10756... |
//// ////
|
//// ////
|
//// Test transmit packets after TX under-run on each packet's ////
|
//// Test transmit packets after TX under-run on each packet's ////
|
//// byte at 2 TX buffer decriptors ( 100Mbps ). ////
|
//// byte at 2 TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 21) // without padding
|
if (test_num == 21) //
|
begin
|
begin
|
// TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )
|
// TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )
|
test_name = "TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )";
|
test_name = "TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )";
|
`TIME;
|
`TIME;
|
$display(" TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )");
|
$display(" TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )");
|
| Line 10775... |
Line 10861... |
else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
|
else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
|
begin
|
begin
|
disable wait_fr1;
|
disable wait_fr1;
|
if (frame_ended == 1)
|
if (frame_ended == 1)
|
begin
|
begin
|
$display("(%0t) no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
|
$display(" ->no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
|
$time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
|
({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
|
no_underrun = 1;
|
no_underrun = 1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wait (frame_ended == 1);
|
wait (frame_ended == 1);
|
$display("(%0t) under-run on %0d. byte",
|
$display(" ->under-run on %0d. byte",
|
$time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
|
({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
|
no_underrun = 0;
|
no_underrun = 0;
|
end
|
end
|
end
|
end
|
repeat (2) @(posedge wb_clk);
|
repeat (2) @(posedge wb_clk);
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
| Line 10823... |
Line 10909... |
// WAIT FOR FIRST TRANSMIT
|
// WAIT FOR FIRST TRANSMIT
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
wait (MTxEn === 1'b1); // start first transmit
|
wait (MTxEn === 1'b1); // start first transmit
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end first transmit
|
wait (MTxEn === 1'b0); // end first transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
| Line 11177... |
Line 11264... |
$display("MAC FULL DUPLEX RECEIVE TEST");
|
$display("MAC FULL DUPLEX RECEIVE TEST");
|
fail = 0;
|
fail = 0;
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
//reset_mac;
|
|
//reset_mii;
|
|
// set wb slave response
|
// set wb slave response
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
/*
|
/*
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
| Line 11261... |
Line 11345... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test no receive when all buffers are TX ( 10Mbps ). ////
|
//// Test no receive when all buffers are TX ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) // Test no receive when all buffers are TX ( 10Mbps ).
|
if (test_num == 0) //
|
begin
|
begin
|
// TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
|
// TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
|
test_name = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
|
test_name = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
|
`TIME; $display(" TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
|
`TIME; $display(" TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
|
|
|
| Line 11351... |
Line 11435... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test no receive when all buffers are TX ( 100Mbps ). ////
|
//// Test no receive when all buffers are TX ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) // Test no receive when all buffers are TX ( 100Mbps ).
|
if (test_num == 1) //
|
begin
|
begin
|
// TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
|
// TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
|
test_name = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
|
test_name = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
|
`TIME; $display(" TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
|
`TIME; $display(" TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
|
|
|
| Line 11442... |
Line 11526... |
//// ////
|
//// ////
|
//// Test receive packet synchronization with receive ////
|
//// Test receive packet synchronization with receive ////
|
//// disable/enable ( 10Mbps ). ////
|
//// disable/enable ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) // Test no receive when all buffers are TX ( 10Mbps ).
|
if (test_num == 2) //
|
begin
|
begin
|
// TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
|
// TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
|
test_name = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
|
test_name = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
|
`TIME; $display(" TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
|
`TIME; $display(" TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
|
|
|
| Line 11629... |
Line 11713... |
if (tmp_data[31])
|
if (tmp_data[31])
|
$display(" ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
|
$display(" ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
|
else
|
else
|
$display(" ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
|
$display(" ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
|
end
|
end
|
|
// check FB, etc.
|
|
if (tmp_bd[31:0] !== 32'h0000_E000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status of NOT received packet is not correct: %0h", tmp_bd[31:0]);
|
|
test_fail("RX buffer descriptor status of NOT received packet is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// else // (tmp_bd[15] === 0) - check FB, packet, etc.
|
|
end
|
|
else // (num_of_frames[0] == 1'b1)
|
|
begin
|
|
if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
|
|
begin // check NOTHING
|
|
`TIME; $display("*E RX packet should be accepted, buffer descriptor is not correct: %0h", tmp_bd[31:0]);
|
|
test_fail("RX packet should be accepted, buffer descriptor is not correct");
|
|
fail = fail + 1;
|
end
|
end
|
|
// else // (tmp_bd[15] === 0) - check FB, packet, etc.
|
end
|
end
|
if (stop_checking_frame == 0)
|
if (stop_checking_frame == 0)
|
disable send_packet0;
|
disable send_packet1;
|
end
|
end
|
join
|
join
|
// ONLY IF packet was received!
|
// ONLY IF packet was received!
|
if (tmp_bd[15] === 0)
|
if (tmp_bd[15] === 0)
|
begin
|
begin
|
| Line 11792... |
Line 11894... |
//// ////
|
//// ////
|
//// Test receive packet synchronization with receive ////
|
//// Test receive packet synchronization with receive ////
|
//// disable/enable ( 100Mbps ). ////
|
//// disable/enable ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) // Test no receive when all buffers are TX ( 100Mbps ).
|
if (test_num == 3) //
|
begin
|
begin
|
// TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
|
// TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
|
test_name = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
|
test_name = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
|
`TIME; $display(" TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
|
`TIME; $display(" TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
|
|
|
| Line 11880... |
Line 11982... |
// detect carrier sense in FD and set collision
|
// detect carrier sense in FD and set collision
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.collision(1);
|
eth_phy.collision(1);
|
end
|
end
|
endcase
|
endcase
|
//if (first_fr_received == 0)
|
|
//begin
|
|
// check_rx_bd(118, data);
|
|
// wait (wbm_working == 0);
|
|
// wbm_read((`TX_BD_BASE + (118 * 8) + 4), tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// $display("RX BD set : %h, %h", data, tmp);
|
|
//end
|
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(118);
|
set_rx_bd_wrap(118);
|
set_rx_bd_empty(118, 118);
|
set_rx_bd_empty(118, 118);
|
check_frame = 0;
|
check_frame = 0;
|
stop_checking_frame = 0;
|
stop_checking_frame = 0;
|
| Line 11914... |
Line 12009... |
wbm_subseq_waits = 4'h0;
|
wbm_subseq_waits = 4'h0;
|
#1 wait (wbm_working == 0);
|
#1 wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
|
$display("mama 2, num_of_frames=%0h", num_of_frames);
|
|
end
|
end
|
end
|
end
|
begin // send a packet from PHY RX
|
begin // send a packet from PHY RX
|
repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
|
repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
|
if (num_of_frames[1] == 1'b0)
|
if (num_of_frames[1] == 1'b0)
|
| Line 11934... |
Line 12028... |
end
|
end
|
begin: send_packet1
|
begin: send_packet1
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b0); // end transmit
|
wait (MRxDV === 1'b0); // end transmit
|
check_frame = 1;
|
check_frame = 1;
|
$display("mama 3");
|
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
repeat(15) @(posedge wb_clk);
|
repeat(15) @(posedge wb_clk);
|
stop_checking_frame = 1;
|
stop_checking_frame = 1;
|
end
|
end
|
begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
|
begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
|
@(posedge eth_sl_wb_ack_o or posedge MRxDV);
|
@(posedge eth_sl_wb_ack_o or posedge MRxDV);
|
$display("mama 4");
|
|
if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
|
if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
|
begin
|
begin
|
tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
|
tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
|
$display("mama 4_1");
|
|
end
|
end
|
else if (MRxDV === 1'b1)
|
else if (MRxDV === 1'b1)
|
begin
|
begin
|
while (eth_sl_wb_ack_o === 1'b0)
|
while (eth_sl_wb_ack_o === 1'b0)
|
begin
|
begin
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
tmp_data = tmp_data + 1;
|
tmp_data = tmp_data + 1;
|
end
|
end
|
tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
|
tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
|
$display("mama 4_2");
|
|
end
|
end
|
else if (eth_sl_wb_ack_o === 1'b1)
|
else if (eth_sl_wb_ack_o === 1'b1)
|
begin
|
begin
|
@(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
|
@(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
|
while (MRxDV === 1'b0)
|
while (MRxDV === 1'b0)
|
begin
|
begin
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
|
tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
|
end
|
end
|
$display("mama 4_3");
|
|
end
|
end
|
end
|
end
|
begin // check packet
|
begin // check packet
|
wait (check_frame == 1);
|
wait (check_frame == 1);
|
check_rx_bd(118, tmp_bd);
|
check_rx_bd(118, tmp_bd);
|
while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
|
while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
|
begin
|
begin
|
#1 check_rx_bd(118, tmp_bd);
|
#1 check_rx_bd(118, tmp_bd);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
$display("mama 5, tmp_bd=%0h", tmp_bd);
|
|
if (num_of_frames[0] == 1'b0)
|
if (num_of_frames[0] == 1'b0)
|
begin
|
begin
|
if (tmp_bd[15] === 1)
|
if (tmp_bd[15] === 1)
|
begin
|
begin
|
if (first_fr_received == 1)
|
if (first_fr_received == 1)
|
| Line 11994... |
Line 12082... |
$display(" ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
|
$display(" ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
|
else
|
else
|
$display(" ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
|
$display(" ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
|
end
|
end
|
// check FB, etc.
|
// check FB, etc.
|
|
if (tmp_bd[31:0] !== 32'h0000_E000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status of NOT received packet is not correct: %0h", tmp_bd[31:0]);
|
|
test_fail("RX buffer descriptor status of NOT received packet is not correct");
|
|
fail = fail + 1;
|
end
|
end
|
else // (tmp_bd[15] === 0)
|
|
begin // check FB, packet, etc.
|
|
|
|
end
|
end
|
$display("mama 5_1");
|
// else // (tmp_bd[15] === 0) - check FB, packet, etc.
|
end
|
end
|
else // (num_of_frames[0] == 1'b1)
|
else // (num_of_frames[0] == 1'b1)
|
begin
|
begin
|
if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
|
if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
|
begin // check NOTHING
|
begin // check NOTHING
|
|
`TIME; $display("*E RX packet should be accepted, buffer descriptor is not correct: %0h", tmp_bd[31:0]);
|
end
|
test_fail("RX packet should be accepted, buffer descriptor is not correct");
|
else // (tmp_bd[15] === 0)
|
fail = fail + 1;
|
begin // check FB, packet, etc.
|
|
|
|
end
|
end
|
$display("mama 5_2");
|
// else // (tmp_bd[15] === 0) - check FB, packet, etc.
|
end
|
end
|
if (stop_checking_frame == 0)
|
if (stop_checking_frame == 0)
|
disable send_packet1;
|
disable send_packet1;
|
end
|
end
|
join
|
join
|
// ONLY IF packet was received!
|
// ONLY IF packet was received!
|
$display("mama 6");
|
|
if (tmp_bd[15] === 0)
|
if (tmp_bd[15] === 0)
|
begin
|
begin
|
// check length of a PACKET
|
// check length of a PACKET
|
if (tmp_bd[31:16] != (i_length + 4))
|
if (tmp_bd[31:16] != (i_length + 4))
|
begin
|
begin
|
| Line 12192... |
Line 12278... |
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO,// | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare two packets of MAXFL length
|
// prepare two packets of MAXFL length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
st_data = 8'h0F;
|
st_data = 8'h0F;
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
st_data = 8'h1A;
|
st_data = 8'h1A;
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
| Line 12483... |
Line 12569... |
//// ////
|
//// ////
|
//// Test receive packets form MINFL to MAXFL sizes at ////
|
//// Test receive packets form MINFL to MAXFL sizes at ////
|
//// one RX buffer decriptor ( 100Mbps ). ////
|
//// one RX buffer decriptor ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 5) // Test no receive when all buffers are TX ( 100Mbps ).
|
if (test_num == 5) //
|
begin
|
begin
|
// TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
|
// TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
|
test_name = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
|
test_name = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
|
`TIME; $display(" TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
|
`TIME; $display(" TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
|
|
|
| Line 12795... |
Line 12881... |
if (test_num == 6) //
|
if (test_num == 6) //
|
begin
|
begin
|
// TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
|
// TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
|
test_name = "TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )";
|
test_name = "TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )");
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
max_tmp = 0;
|
|
min_tmp = 0;
|
|
num_of_frames = 0;
|
|
num_of_bd = 0;
|
|
// set maximum RX buffer descriptors (128) - must be set before RX enable
|
// set maximum RX buffer descriptors (128) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 12825... |
Line 12898... |
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
st_data = 8'hAC;
|
st_data = 8'hAC;
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
st_data = 8'h35;
|
st_data = 8'h35;
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
|
num_of_frames = 0;
|
|
num_of_bd = 0;
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 12954... |
Line 13029... |
end
|
end
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(127);
|
set_rx_bd_wrap(127);
|
end
|
end
|
// after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
|
// after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
|
else if ((num_of_frames - 8) == 20) // 128
|
else if ((num_of_frames - 8) == 128)
|
begin
|
begin
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
begin
|
begin
|
| Line 13248... |
Line 13323... |
if (test_num == 7) //
|
if (test_num == 7) //
|
begin
|
begin
|
// TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
|
// TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
|
test_name = "TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )";
|
test_name = "TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )");
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
max_tmp = 0;
|
|
min_tmp = 0;
|
|
num_of_frames = 0;
|
|
num_of_bd = 0;
|
|
// set maximum RX buffer descriptors (128) - must be set before RX enable
|
// set maximum RX buffer descriptors (128) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 13278... |
Line 13340... |
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
st_data = 8'hAC;
|
st_data = 8'hAC;
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
st_data = 8'h35;
|
st_data = 8'h35;
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
|
num_of_frames = 0;
|
|
num_of_bd = 0;
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 13407... |
Line 13471... |
end
|
end
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(127);
|
set_rx_bd_wrap(127);
|
end
|
end
|
// after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
|
// after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
|
else if ((num_of_frames - 8) == 20) // 128
|
else if ((num_of_frames - 8) == 128)
|
begin
|
begin
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
begin
|
begin
|
| Line 13697... |
Line 13761... |
//// 8 RX buffer decriptors ( 10Mbps ). ////
|
//// 8 RX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 8) //
|
if (test_num == 8) //
|
begin
|
begin
|
// TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )
|
// TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )
|
test_name = "TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )";
|
test_name = "TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )";
|
`TIME; $display(" TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )");
|
`TIME; $display(" TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )");
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
max_tmp = 0;
|
|
min_tmp = 0;
|
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 14074... |
Line 14127... |
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
|
else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6004) && // wrap bit
|
if ( (data[15:0] !== 16'h6084) && // wrap bit
|
(data[15:0] !== 16'h4004) ) // without wrap bit
|
(data[15:0] !== 16'h4084) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
|
else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6006) && // wrap bit
|
if ( (data[15:0] !== 16'h6086) && // wrap bit
|
(data[15:0] !== 16'h4006) ) // without wrap bit
|
(data[15:0] !== 16'h4086) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 14240... |
Line 14293... |
//// 8 RX buffer decriptors ( 100Mbps ). ////
|
//// 8 RX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 9) //
|
if (test_num == 9) //
|
begin
|
begin
|
// TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )
|
// TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )
|
test_name = "TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )";
|
test_name = "TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )";
|
`TIME; $display(" TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )");
|
`TIME; $display(" TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )");
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// reset MAC and MII LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
max_tmp = 0;
|
|
min_tmp = 0;
|
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 14616... |
Line 14658... |
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
|
else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6004) && // wrap bit
|
if ( (data[15:0] !== 16'h6084) && // wrap bit
|
(data[15:0] !== 16'h4004) ) // without wrap bit
|
(data[15:0] !== 16'h4084) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
|
else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6006) && // wrap bit
|
if ( (data[15:0] !== 16'h6086) && // wrap bit
|
(data[15:0] !== 16'h4006) ) // without wrap bit
|
(data[15:0] !== 16'h4086) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 14776... |
Line 14818... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packet synchronization with receive ////
|
//// Test receive packets at one RX BD and ////
|
//// disable/enable ( 10Mbps ). ////
|
//// check addresses ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 10) // Test no receive when all buffers are TX ( 10Mbps ).
|
if (test_num == 10) //
|
begin
|
begin
|
// TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
|
// TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )
|
test_name = "TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
|
test_name = "TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )";
|
`TIME; $display(" TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
|
`TIME; $display(" TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )");
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
end
|
end
|
|
|
|
// write to phy's control register for 10Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 10;
|
|
|
////////////////////////////////////////////////////////////////////
|
num_of_frames = 0;
|
//// ////
|
i_length = 64;
|
//// Test receive packet synchronization with receive ////
|
while (num_of_frames < 8)
|
//// disable/enable ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 12) // Test no receive when all buffers are TX ( 10Mbps ).
|
|
begin
|
begin
|
// TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
|
// not detect carrier sense in FD and no collision
|
test_name = "TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
`TIME; $display(" TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
|
eth_phy.collision(0);
|
|
case (num_of_frames)
|
|
0: // unicast + PRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet is going to be received with PRO bit (wrap at 1st BD)");
|
end
|
end
|
|
1: // unicast
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packet synchronization with receive ////
|
|
//// disable/enable ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 14) // Test no receive when all buffers are TX ( 10Mbps ).
|
|
begin
|
begin
|
// TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
|
// enable interrupt generation
|
test_name = "TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
`TIME; $display(" TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h12;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet is going to be received without PRO bit (wrap at 1st BD)");
|
end
|
end
|
|
2: // wrong unicast + PRO
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packet synchronization with receive ////
|
|
//// disable/enable ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 16) // Test no receive when all buffers are TX ( 10Mbps ).
|
|
begin
|
begin
|
// TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
|
// enable interrupt generation
|
test_name = "TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
`TIME; $display(" TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h31;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet is going to be received with PRO bit (wrap at 1st BD)");
|
end
|
end
|
|
3: // wrong unicast
|
|
begin
|
|
// enable interrupt generation
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD)");
|
end
|
end
|
endtask // test_mac_full_duplex_receive
|
4: // broadcast + PRO + ~BRO
|
|
|
|
|
task test_mac_full_duplex_flow_control;
|
|
input [31:0] start_task;
|
|
input [31:0] end_task;
|
|
integer bit_start_1;
|
|
integer bit_end_1;
|
|
integer bit_start_2;
|
|
integer bit_end_2;
|
|
integer num_of_reg;
|
|
integer num_of_frames;
|
|
integer num_of_rx_frames;
|
|
integer num_of_bd;
|
|
integer i_addr;
|
|
integer i_data;
|
|
integer i_length;
|
|
integer tmp_len;
|
|
integer tmp_bd;
|
|
integer tmp_bd_num;
|
|
integer tmp_data;
|
|
integer tmp_ipgt;
|
|
integer test_num;
|
|
integer rx_len;
|
|
integer tx_len;
|
|
reg [31:0] tx_bd_num;
|
|
reg [31:0] rx_bd_num;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
|
|
integer i;
|
|
integer i1;
|
|
integer i2;
|
|
integer i3;
|
|
integer fail;
|
|
integer speed;
|
|
integer mac_hi_addr;
|
|
integer mac_lo_addr;
|
|
reg frame_started;
|
|
reg frame_ended;
|
|
reg wait_for_frame;
|
|
reg [31:0] addr;
|
|
reg [31:0] data;
|
|
reg [31:0] tmp;
|
|
reg [ 7:0] st_data;
|
|
reg [15:0] max_tmp;
|
|
reg [15:0] min_tmp;
|
|
reg PassAll;
|
|
reg RxFlow;
|
|
reg enable_irq_in_rxbd;
|
|
reg [15:0] pause_value;
|
|
|
|
begin
|
begin
|
// MAC FULL DUPLEX FLOW CONTROL TEST
|
// enable interrupt generation
|
test_heading("MAC FULL DUPLEX FLOW CONTROL TEST");
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
$display(" ");
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
$display("MAC FULL DUPLEX FLOW CONTROL TEST");
|
wait (wbm_working == 0);
|
fail = 0;
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// reset MAC registers
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
hard_reset;
|
wait (wbm_working == 0);
|
// reset MAC and MII LOGIC with soft reset
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
//reset_mac;
|
`ETH_MODER_PRO,
|
//reset_mii;
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set wb slave response
|
// set Destination address - Byte 0 sent first
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
/*
|
wait (wbm_working == 0);
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
-------------------------------------------------------------------------------------
|
// prepare packet
|
set_tx_bd
|
st_data = 8'h84;
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
set_tx_bd_wrap
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
(tx_bd_num_end[6:0]);
|
$display(" Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)");
|
set_tx_bd_ready
|
end
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
5: // broadcast + ~BRO
|
check_tx_bd
|
begin
|
(tx_bd_num_start[6:0], tx_bd_status[31:0]);
|
// enable interrupt generation
|
clear_tx_bd
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
TASKS for set and control RX buffer descriptors:
|
wbm_write(`ETH_MODER, 32'h0,
|
------------------------------------------------
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
set_rx_bd
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
|
wait (wbm_working == 0);
|
set_rx_bd_wrap
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG,
|
(rx_bd_num_end[6:0]);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
set_rx_bd_empty
|
// set Destination address - Byte 0 sent first
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
wait (wbm_working == 0);
|
check_rx_bd
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
(rx_bd_num_end[6:0], rx_bd_status);
|
wait (wbm_working == 0);
|
clear_rx_bd
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
// prepare packet
|
|
st_data = 8'h48;
|
TASKS for set and check TX packets:
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
-----------------------------------
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
set_tx_packet
|
$display(" Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD)");
|
(txpnt[31:0], len[15:0], eth_start_data[7:0]);
|
end
|
check_tx_packet
|
6: // broadcast + PRO + BRO
|
(txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
|
begin
|
|
// enable interrupt generation
|
TASKS for set and check RX packets:
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
-----------------------------------
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
set_rx_packet
|
wait (wbm_working == 0);
|
(rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
|
wbm_write(`ETH_MODER, 32'h0,
|
check_rx_packet
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
(rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
TASKS for append and check CRC to/of TX packet:
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
-----------------------------------------------
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
append_tx_crc
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
(txpnt_wb[31:0], len[15:0], negated_crc);
|
// set Destination address - Byte 0 sent first
|
check_tx_crc
|
wait (wbm_working == 0);
|
(txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h30;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
7: // broadcast + BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h04;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin: wait_for_rec0
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
while (data[15] === 1)
|
|
begin
|
|
#1 check_rx_bd(127, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
disable check_wait_for_rec0;
|
|
$display(" ->packet received");
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
begin: check_wait_for_rec0
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(50) @(posedge wb_clk);
|
|
wait (wbm_working == 0);
|
|
disable wait_for_rec0;
|
|
$display(" ->packet NOT received");
|
|
end
|
|
join
|
|
// PACKET checking
|
|
wait (wbm_working == 0);
|
|
check_rx_bd(127, data);
|
|
case (num_of_frames)
|
|
0, 1, 4, 5:
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h6000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
2, 6:
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h6080)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
3, 7:
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hE000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// clear RX buffer descriptor
|
|
clear_rx_bd(127, 127);
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
|
|
--------------------------------------------------------------------------------
|
|
append_rx_crc
|
|
(rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
|
|
*/
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
|
//// test_mac_full_duplex_flow_control: ////
|
|
//// ////
|
//// ////
|
//// 0: Test ////
|
//// Test receive packets at one RX BD and ////
|
|
//// check addresses ( 100Mbps ). ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 11) //
|
|
begin
|
|
// TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )
|
|
test_name = "TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )";
|
|
`TIME; $display(" TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )");
|
|
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// write to phy's control register for 100Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 100;
|
|
|
|
num_of_frames = 0;
|
|
i_length = 64;
|
|
while (num_of_frames < 8)
|
|
begin
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
case (num_of_frames)
|
|
0: // unicast + PRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet is going to be received with PRO bit (wrap at 1st BD)");
|
|
end
|
|
1: // unicast
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h12;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet is going to be received without PRO bit (wrap at 1st BD)");
|
|
end
|
|
2: // wrong unicast + PRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h31;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet is going to be received with PRO bit (wrap at 1st BD)");
|
|
end
|
|
3: // wrong unicast
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD)");
|
|
end
|
|
4: // broadcast + PRO + ~BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h84;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
5: // broadcast + ~BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h48;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
6: // broadcast + PRO + BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h30;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
7: // broadcast + BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h04;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin: wait_for_rec1
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
while (data[15] === 1)
|
|
begin
|
|
#1 check_rx_bd(127, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
disable check_wait_for_rec1;
|
|
$display(" ->packet received");
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
begin: check_wait_for_rec1
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(50) @(posedge wb_clk);
|
|
wait (wbm_working == 0);
|
|
disable wait_for_rec1;
|
|
$display(" ->packet NOT received");
|
|
end
|
|
join
|
|
// PACKET checking
|
|
wait (wbm_working == 0);
|
|
check_rx_bd(127, data);
|
|
case (num_of_frames)
|
|
0, 1, 4, 5:
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h6000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
2, 6:
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h6080)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
3, 7:
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hE000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// clear RX buffer descriptor
|
|
clear_rx_bd(127, 127);
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packets at 8 RX BD with ////
|
|
//// RX FIFO and RX BD overrun ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 12) //
|
|
begin
|
|
// TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )
|
|
test_name = "TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )";
|
|
`TIME; $display(" TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )");
|
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 10Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 10;
|
|
|
|
// enable interrupt generation
|
|
set_rx_bd(120, 127, 1'b1, `MEMORY_BASE);
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
num_of_frames = 0;
|
|
while (num_of_frames < 11)
|
|
begin
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
if (num_of_frames < 2)
|
|
num_of_bd = 120 + num_of_frames;
|
|
else if (num_of_frames < 9)
|
|
num_of_bd = 120 + num_of_frames - 1;
|
|
else
|
|
num_of_bd = 120;
|
|
case (num_of_frames)
|
|
0:
|
|
begin
|
|
// prepare packet
|
|
i_length = 60;
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
3:
|
|
begin
|
|
// prepare packet
|
|
i_length = 68;
|
|
st_data = 8'h01;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
6:
|
|
begin
|
|
// prepare packet
|
|
i_length = 80;
|
|
st_data = 8'hA1;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
10:
|
|
begin
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// DISPLAYS
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
$display(" packet shoud be successfuly received");
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
$display(" packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun");
|
|
end
|
|
2, 4, 6: // RX FIFO overrun
|
|
begin
|
|
$display(" packet should NOT be received - RX FIFO overrun");
|
|
end
|
|
9: // RX BD overrun
|
|
begin
|
|
$display(" packet should NOT be received - RX FIFO overrun due to lack of RX BDs");
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin: set_no_resp2
|
|
if ((num_of_frames == 1) || (num_of_frames == 4)) // RX FIFO overrun!
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
if (num_of_frames == 6) // RX FIFO overrun!
|
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (eth_ma_wb_ack_i === 1'b1) // WB transfer
|
|
wait (eth_ma_wb_ack_i === 1'b0) // WB transfer
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
end
|
|
end
|
|
begin: wait_for_rec2
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
//$display("Num of RX BD = %d, RX BD %0d = %h", num_of_bd, num_of_bd, data);
|
|
if (((data[15] !== 1) && (num_of_frames != 9)) || // RX BD must be Empty
|
|
((data[15] !== 0) && (num_of_frames == 9))) // RX BD must NOT be Empty - RX BD overrun!!!
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
while (((data[15] === 1) && (num_of_frames != 9)) ||
|
|
((data[15] === 0) && (num_of_frames == 9)))
|
|
begin
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
disable check_wait_for_rec2;
|
|
disable set_no_resp2;
|
|
$display(" ->packet received");
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
begin: check_wait_for_rec2
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(50) @(posedge wb_clk);
|
|
wait (wbm_working == 0);
|
|
disable wait_for_rec2;
|
|
disable set_no_resp2;
|
|
$display(" ->packet NOT received");
|
|
end
|
|
join
|
|
// PACKET checking
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (((data[15:0] !== 16'h4000) && (num_of_bd != 127)) || // without wrap bit
|
|
((data[15:0] !== 16'h6000) && (num_of_bd == 127)))
|
|
begin
|
|
`TIME;
|
|
if (num_of_bd != 127)
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 6000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
2: // RX FIFO overrun & previous packet written
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
$display(" ->previous packet written into MEM");
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
end
|
|
4, 6: // RX FIFO overrun
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4040)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4040", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
end
|
|
9: // RX BD overrun
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
// NOT checked since BD value is from first packet - RX BD overrun
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_BUSY) !== `ETH_INT_BUSY)
|
|
begin
|
|
`TIME; $display("*E Interrupt BUSY was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt BUSY was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_BUSY)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except BUSY) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except BUSY) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packets at 8 RX BD with ////
|
|
//// RX FIFO and RX BD overrun ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 13) //
|
|
begin
|
|
// TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )
|
|
test_name = "TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )";
|
|
`TIME; $display(" TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )");
|
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 100Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 100;
|
|
|
|
// enable interrupt generation
|
|
set_rx_bd(120, 127, 1'b1, `MEMORY_BASE);
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
|
|
num_of_frames = 0;
|
|
while (num_of_frames < 11)
|
|
begin
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
if (num_of_frames < 2)
|
|
num_of_bd = 120 + num_of_frames;
|
|
else if (num_of_frames < 9)
|
|
num_of_bd = 120 + num_of_frames - 1;
|
|
else
|
|
num_of_bd = 120;
|
|
case (num_of_frames)
|
|
0:
|
|
begin
|
|
// prepare packet
|
|
i_length = 60;
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
3:
|
|
begin
|
|
// prepare packet
|
|
i_length = 68;
|
|
st_data = 8'h01;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
6:
|
|
begin
|
|
// prepare packet
|
|
i_length = 80;
|
|
st_data = 8'hA1;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
10:
|
|
begin
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// DISPLAYS
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
$display(" packet shoud be successfuly received");
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
$display(" packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun");
|
|
end
|
|
2, 4, 6: // RX FIFO overrun
|
|
begin
|
|
$display(" packet should NOT be received - RX FIFO overrun");
|
|
end
|
|
9: // RX BD overrun
|
|
begin
|
|
$display(" packet should NOT be received - RX FIFO overrun due to lack of RX BDs");
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin: set_no_resp3
|
|
if ((num_of_frames == 1) || (num_of_frames == 4)) // RX FIFO overrun!
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
if (num_of_frames == 6) // RX FIFO overrun!
|
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (eth_ma_wb_ack_i === 1'b1) // WB transfer
|
|
wait (eth_ma_wb_ack_i === 1'b0) // WB transfer
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
end
|
|
end
|
|
begin: wait_for_rec3
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
if (((data[15] !== 1) && (num_of_frames != 9)) || // RX BD must be Empty
|
|
((data[15] !== 0) && (num_of_frames == 9))) // RX BD must NOT be Empty - RX BD overrun!!!
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
while (((data[15] === 1) && (num_of_frames != 9)) ||
|
|
((data[15] === 0) && (num_of_frames == 9)))
|
|
begin
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
disable check_wait_for_rec3;
|
|
disable set_no_resp3;
|
|
$display(" ->packet received");
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
begin: check_wait_for_rec3
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(50) @(posedge wb_clk);
|
|
wait (wbm_working == 0);
|
|
disable wait_for_rec3;
|
|
disable set_no_resp3;
|
|
$display(" ->packet NOT received");
|
|
end
|
|
join
|
|
// PACKET checking
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (((data[15:0] !== 16'h4000) && (num_of_bd != 127)) || // without wrap bit
|
|
((data[15:0] !== 16'h6000) && (num_of_bd == 127)))
|
|
begin
|
|
`TIME;
|
|
if (num_of_bd != 127)
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 6000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
2: // RX FIFO overrun & previous packet written
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
$display(" ->previous packet written into MEM");
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
end
|
|
4, 6: // RX FIFO overrun
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4040)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4040", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
end
|
|
9: // RX BD overrun
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
// NOT checked since BD value is from first packet - RX BD overrun
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_BUSY) !== `ETH_INT_BUSY)
|
|
begin
|
|
`TIME; $display("*E Interrupt BUSY was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt BUSY was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_BUSY)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except BUSY) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except BUSY) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
|
|
end
|
|
endtask // test_mac_full_duplex_receive
|
|
|
|
|
|
task test_mac_full_duplex_flow_control;
|
|
input [31:0] start_task;
|
|
input [31:0] end_task;
|
|
integer bit_start_1;
|
|
integer bit_end_1;
|
|
integer bit_start_2;
|
|
integer bit_end_2;
|
|
integer num_of_reg;
|
|
integer num_of_frames;
|
|
integer num_of_rx_frames;
|
|
integer num_of_bd;
|
|
integer i_addr;
|
|
integer i_data;
|
|
integer i_length;
|
|
integer tmp_len;
|
|
integer tmp_bd;
|
|
integer tmp_bd_num;
|
|
integer tmp_data;
|
|
integer tmp_ipgt;
|
|
integer test_num;
|
|
integer rx_len;
|
|
integer tx_len;
|
|
reg [31:0] tx_bd_num;
|
|
reg [31:0] rx_bd_num;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
|
|
integer i;
|
|
integer i1;
|
|
integer i2;
|
|
integer i3;
|
|
integer fail;
|
|
integer speed;
|
|
integer mac_hi_addr;
|
|
integer mac_lo_addr;
|
|
reg frame_started;
|
|
reg frame_ended;
|
|
reg wait_for_frame;
|
|
reg [31:0] addr;
|
|
reg [31:0] data;
|
|
reg [31:0] tmp;
|
|
reg [ 7:0] st_data;
|
|
reg [15:0] max_tmp;
|
|
reg [15:0] min_tmp;
|
|
reg PassAll;
|
|
reg RxFlow;
|
|
reg enable_irq_in_rxbd;
|
|
reg [15:0] pause_value;
|
|
|
|
begin
|
|
// MAC FULL DUPLEX FLOW CONTROL TEST
|
|
test_heading("MAC FULL DUPLEX FLOW CONTROL TEST");
|
|
$display(" ");
|
|
$display("MAC FULL DUPLEX FLOW CONTROL TEST");
|
|
fail = 0;
|
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
/*
|
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
|
-------------------------------------------------------------------------------------
|
|
set_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
|
|
set_tx_bd_wrap
|
|
(tx_bd_num_end[6:0]);
|
|
set_tx_bd_ready
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
check_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_status[31:0]);
|
|
clear_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and control RX buffer descriptors:
|
|
------------------------------------------------
|
|
set_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
|
|
set_rx_bd_wrap
|
|
(rx_bd_num_end[6:0]);
|
|
set_rx_bd_empty
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
check_rx_bd
|
|
(rx_bd_num_end[6:0], rx_bd_status);
|
|
clear_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and check TX packets:
|
|
-----------------------------------
|
|
set_tx_packet
|
|
(txpnt[31:0], len[15:0], eth_start_data[7:0]);
|
|
check_tx_packet
|
|
(txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
|
|
|
|
TASKS for set and check RX packets:
|
|
-----------------------------------
|
|
set_rx_packet
|
|
(rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
|
|
check_rx_packet
|
|
(rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
|
|
|
|
TASKS for append and check CRC to/of TX packet:
|
|
-----------------------------------------------
|
|
append_tx_crc
|
|
(txpnt_wb[31:0], len[15:0], negated_crc);
|
|
check_tx_crc
|
|
(txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
|
|
|
|
TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
|
|
--------------------------------------------------------------------------------
|
|
append_rx_crc
|
|
(rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
|
|
*/
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// test_mac_full_duplex_flow_control: ////
|
|
//// ////
|
|
//// 0: Test ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
|
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
|
begin
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test inserts control frames while transmitting normal ////
|
|
//// frames. Using 4 TX buffer decriptors ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 0) //
|
|
begin
|
|
// TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )
|
|
test_name = "TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )";
|
|
`TIME; $display(" TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )");
|
|
|
|
// reset MAC completely
|
|
hard_reset;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
max_tmp = 0;
|
|
min_tmp = 0;
|
|
// set 4 TX buffer descriptors - must be set before TX enable
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable TX, set full-duplex mode, padding and CRC appending
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable TX flow control
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// Set MAC address
|
|
mac_hi_addr = 32'h00000001;
|
|
mac_lo_addr = 32'h02030405;
|
|
wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// prepare two packets of MAXFL length
|
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
|
min_tmp = tmp[31:16];
|
|
st_data = 8'h34;
|
|
set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
|
|
st_data = 8'h56;
|
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// write to phy's control register for 10Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 10;
|
|
|
|
frame_started = 0;
|
|
num_of_frames = 0;
|
|
num_of_bd = 0;
|
|
i_length = 0; // 0;
|
|
// Initialize one part of memory with data of control packet
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
|
|
// append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0); // CRC is appended after the data
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame will be sent while no other transmission is in progress.//
|
|
// TXC interrupt won't be unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
|
test_fail("IRQ already pending!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E IRQ already pending!");
|
|
end
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// Request sending the control frame with pause value = 0x1111
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait for transmission to come over
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time
|
|
// check interrupt
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
|
test_fail("TXC IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
end
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set because TXC irq is masked!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
|
|
end
|
|
// Clear TXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
// check transmited TX packet
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong CRC of the transmitted packet");
|
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame will be sent while no other transmission is in progress.//
|
|
// TXC interrupt is unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// unmask all interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
|
test_fail("IRQ already pending!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E IRQ already pending!");
|
|
end
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
// unmask only TXC interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// Request sending the control frame with pause value = 0x2222
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF); // Just for data test
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait for transmit to come over
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time
|
|
// check INT
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
|
test_fail("TXC IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
end
|
|
if (!wb_int)
|
|
begin
|
|
test_fail("WB INT signal should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should be set!");
|
|
end
|
|
// Clear TXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
// check transmited TX packet
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong CRC of the transmitted packet");
|
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame sending is requested while no other transmission //
|
|
// is in progress. TXC interrupt is unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// unmask all interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
|
test_fail("IRQ already pending!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E IRQ already pending!");
|
|
end
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame request and data send request are both set. At the //
|
|
// beginning control frame request will be faster than data send request, later the opposite. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
for (i=0; i<32; i=i+1)
|
|
begin
|
|
// Request sending the control frame with pause value = 0x5678
|
|
set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
|
|
set_tx_bd_wrap(0);
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
set_tx_bd_ready(0, 0);
|
|
// wait for transmission to start
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
repeat(i) @ (posedge mtx_clk); // We need to wait some time until TX module starts using the data (preamble stage is over)
|
|
// Send control frame request
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF); // Just for data test
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait until transmission is over
|
|
wait (MTxEn === 1'b0); // Wait until data frame transmission is over
|
|
repeat(10) @ (posedge mtx_clk); // wait some time so status is written
|
|
tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
|
|
repeat(10) @ (posedge wb_clk); // wait some time so status is written
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// check interrupt depending on which packet was sent
|
|
if(tmp_len == 64) // Control frame
|
|
begin
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
|
test_fail("TXC IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
`TIME; $display("ETH_INT = 0x%0x", data);
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXB)
|
|
begin
|
|
test_fail("TXB IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXB IRQ should be set!");
|
|
`TIME; $display("ETH_INT = 0x%0x", data);
|
|
end
|
|
end
|
|
// check transmited TX packet
|
|
if(tmp_len == 64) // Control frame
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
else
|
|
check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
if(tmp_len == 64) // Control frame
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
else
|
|
#1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
|
|
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong CRC of the transmitted packet");
|
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// wait for control frame to transmit
|
|
wait (MTxEn === 1'b1); // start transmit of the control frame
|
|
wait (MTxEn === 1'b0); // end transmit of the control frame
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time so status is written
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
|
|
begin
|
|
test_fail("TXC and TXB IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
|
|
end
|
|
if (!wb_int)
|
|
begin
|
|
test_fail("WB INT signal should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should be set!");
|
|
end
|
|
// Clear TXC and TXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
if(tmp_len == 64) // Control frame
|
|
check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
|
|
else
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
if(tmp_len == 64) // Control frame
|
|
#1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
|
|
else
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong CRC of the transmitted packet");
|
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
end // for loop
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test inserts control frames while transmitting normal ////
|
|
//// frames. Using 4 TX buffer decriptors ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 1) //
|
|
begin
|
|
// TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )
|
|
test_name = "TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )";
|
|
`TIME; $display(" TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )");
|
|
|
|
// reset MAC completely
|
|
hard_reset;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
max_tmp = 0;
|
|
min_tmp = 0;
|
|
// set 4 TX buffer descriptors - must be set before TX enable
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable TX, set full-duplex mode, padding and CRC appending
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable TX flow control
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// Set MAC address
|
|
mac_hi_addr = 32'h00000001;
|
|
mac_lo_addr = 32'h02030405;
|
|
wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// prepare two packets of MAXFL length
|
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
|
min_tmp = tmp[31:16];
|
|
st_data = 8'h34;
|
|
set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
|
|
st_data = 8'h56;
|
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// write to phy's control register for 100Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 100;
|
|
|
|
frame_started = 0;
|
|
num_of_frames = 0;
|
|
num_of_bd = 0;
|
|
i_length = 0; // 0;
|
|
// Initialize one part of memory with data of control packet
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
|
|
// append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0); // CRC is appended after the data
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame will be sent while no other transmission is in progress.//
|
|
// TXC interrupt won't be unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
|
test_fail("IRQ already pending!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E IRQ already pending!");
|
|
end
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// Request sending the control frame with pause value = 0x1111
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait for transmission to come over
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time
|
|
// check interrupt
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
|
test_fail("TXC IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
end
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set because TXC irq is masked!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
|
|
end
|
|
// Clear TXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
// check transmited TX packet
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong CRC of the transmitted packet");
|
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame will be sent while no other transmission is in progress.//
|
|
// TXC interrupt is unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// unmask all interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
|
test_fail("IRQ already pending!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E IRQ already pending!");
|
|
end
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
// unmask only TXC interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// Request sending the control frame with pause value = 0x2222
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF); // Just for data test
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait for transmit to come over
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time
|
|
// check INT
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
|
test_fail("TXC IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
end
|
|
if (!wb_int)
|
|
begin
|
|
test_fail("WB INT signal should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should be set!");
|
|
end
|
|
// Clear TXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
// check transmited TX packet
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong CRC of the transmitted packet");
|
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame sending is requested while no other transmission //
|
|
// is in progress. TXC interrupt is unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// unmask all interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
|
test_fail("IRQ already pending!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E IRQ already pending!");
|
|
end
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame request and data send request are both set. At the //
|
|
// beginning control frame request will be faster than data send request, later the opposite. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
for (i=0; i<32; i=i+1)
|
|
begin
|
|
// Request sending the control frame with pause value = 0x5678
|
|
set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
|
|
set_tx_bd_wrap(0);
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
set_tx_bd_ready(0, 0);
|
|
// wait for transmission to start
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
repeat(i) @ (posedge mtx_clk); // We need to wait some time until TX module starts using the data (preamble stage is over)
|
|
// Send control frame request
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF); // Just for data test
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait until transmission is over
|
|
wait (MTxEn === 1'b0); // Wait until data frame transmission is over
|
|
repeat(10) @ (posedge mtx_clk); // wait some time so status is written
|
|
tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
|
|
repeat(10) @ (posedge wb_clk); // wait some time so status is written
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// check interrupt depending on which packet was sent
|
|
|
|
if(tmp_len == 64) // Control frame
|
|
begin
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
|
test_fail("TXC IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
`TIME; $display("ETH_INT = 0x%0x", data);
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXB)
|
|
begin
|
|
test_fail("TXB IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXB IRQ should be set!");
|
|
`TIME; $display("ETH_INT = 0x%0x", data);
|
|
end
|
|
end
|
|
// check transmited TX packet
|
|
if(tmp_len == 64) // Control frame
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
else
|
|
check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
if(tmp_len == 64) // Control frame
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
else
|
|
#1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
|
|
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong CRC of the transmitted packet");
|
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// wait for control frame to transmit
|
|
wait (MTxEn === 1'b1); // start transmit of the control frame
|
|
wait (MTxEn === 1'b0); // end transmit of the control frame
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time so status is written
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
|
|
begin
|
|
test_fail("TXC and TXB IRQ should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
|
|
end
|
|
if (!wb_int)
|
|
begin
|
|
test_fail("WB INT signal should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should be set!");
|
|
end
|
|
// Clear TXC and TXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
|
|
if (wb_int)
|
|
begin
|
|
test_fail("WB INT signal should not be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
|
if(tmp_len == 64) // Control frame
|
|
check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
|
|
else
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
if(tmp_len == 64) // Control frame
|
|
#1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
|
|
else
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
|
begin
|
|
$display("Wrong CRC of the transmitted packet");
|
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
end // for loop
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Receive control frames with PASSALL option turned on and ////
|
|
//// off. Using only one RX buffer decriptor ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 2) //
|
|
begin
|
|
// TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )
|
|
test_name = "TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )";
|
|
`TIME; $display(" TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )");
|
|
|
|
// unmask interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX_FLOW control
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// prepare one packet of 100 bytes long
|
|
// st_data = 8'h1A;
|
|
// set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
|
// append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
|
|
st_data = 8'h01;
|
|
set_tx_packet(`MEMORY_BASE + 64, 100, 8'h01); // length without CRC
|
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
|
|
set_tx_bd_wrap(0);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// write to phy's control register for 10Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 10;
|
|
|
|
// RXB and RXC interrupts masked
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
|
|
for (i=0; i<3; i=i+1)
|
|
begin
|
|
pause_value = i+2;
|
|
set_rx_control_packet(0, pause_value); // CRC already appended
|
|
case (i)
|
|
0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
|
|
begin
|
|
PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
|
|
begin
|
|
PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
|
|
begin
|
|
PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
default:
|
|
begin
|
|
$display("*E We should never get here !!!");
|
|
test_fail("We should never get here !!!");
|
|
fail = fail + 1;
|
|
end
|
|
endcase
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
// set wrap bit and empty bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
// transmit
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
$display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // received pause frame
|
|
repeat(5) @(posedge mrx_clk); // Wait some time so pause is activated.
|
|
repeat(5) @(posedge mtx_clk); // Wait some time so pause is activated.
|
|
set_tx_bd_ready(0, 0); // Request sending the data. Data should not be sent when pause frame was received
|
|
// and RxFlow enabled.
|
|
// When we exit the while loop, status frame is received
|
|
repeat(`ETH_TX_FIFO_DEPTH) @(eth_ma_wb_ack_i); // Waiting until TX fifo is filled.
|
|
repeat(10) @(posedge mtx_clk); // Wait some time for tx start.
|
|
end
|
|
join
|
|
#1 check_rx_bd(127, data);
|
|
// Checking buffer descriptor
|
|
if(PassAll)
|
|
begin
|
|
if(enable_irq_in_rxbd)
|
|
begin
|
|
if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
|
|
begin
|
|
$display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 32'h402100) // Rx BD must not be marked as EMPTY (control frame is received)
|
|
begin
|
|
$display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
|
|
begin
|
|
$display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// Checking if interrupt was generated
|
|
if (wb_int)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
|
|
test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
|
|
fail = fail + 1;
|
|
end
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(RxFlow)
|
|
begin
|
|
if(data !== (`ETH_INT_RXC))
|
|
begin
|
|
test_fail("RXC is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
else if(enable_irq_in_rxbd)
|
|
begin
|
|
if(data !== (`ETH_INT_RXB))
|
|
begin
|
|
test_fail("RXB is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 0)
|
|
begin
|
|
test_fail("Some IRQs is active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
end
|
|
if(RxFlow)
|
|
begin
|
|
if(MTxEn) // If pause frame was received OK, transmission of the data packet should not start
|
|
begin
|
|
`TIME; $display("*E Transmission should not be started because pause frame was received.");
|
|
test_fail("Transmission should not be started because pause frame was received.");
|
|
fail = fail + 1;
|
|
end
|
|
while(pause_value)
|
|
begin
|
|
pause_value=pause_value-1;
|
|
repeat(2*64) @(posedge mtx_clk); // Wait for the time needed for the pause (1 slot).
|
|
if((!pause_value) && (!MTxEn)) // Transmission should be enabled now.
|
|
begin
|
|
`TIME; $display("*E Transmission should be started because pause passed.");
|
|
test_fail("Transmission should be started because pause passed.");
|
|
fail = fail + 1;
|
|
end
|
|
else if((pause_value) && (MTxEn)) // Transmission should not be enabled now.
|
|
begin
|
|
`TIME; $display("*E Transmission should still be paused.");
|
|
test_fail("Transmission should still be paused.");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if(!MTxEn) // Pause frame was not received because RxFlow is turned off.
|
|
begin
|
|
`TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
|
|
test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
wait(wb_int); // Wait antil frame transmission is over and irq generated
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== (`ETH_INT_TXB))
|
|
begin
|
|
test_fail("TXB is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear TXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
// End: Test is irq is set while RXB and RXC interrupts are masked.
|
|
|
|
// Now all interrupts are unmasked. Performing tests again.
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
for (i=0; i<4; i=i+1)
|
|
begin
|
|
pause_value = i+1;
|
|
set_rx_control_packet(0, pause_value); // CRC already appended
|
|
case (i)
|
|
0: // PASSALL = 0, RXFLOW = 0
|
|
begin
|
|
PassAll=0; RxFlow=0;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
1: // PASSALL = 0, RXFLOW = 1
|
|
begin
|
|
PassAll=0; RxFlow=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
2: // PASSALL = 1, RXFLOW = 0
|
|
begin
|
|
PassAll=1; RxFlow=0;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
default: // 3: PASSALL = 1, RXFLOW = 1
|
|
begin
|
|
PassAll=1; RxFlow=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 1 and RXFLOW = 1
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
endcase
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
// set wrap bit and empty bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
// transmit
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin
|
|
#1 check_rx_bd(127, data);
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
$display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(50) @(posedge mrx_clk); // Wait some time so frame is received and
|
|
repeat (100) @(posedge wb_clk); // status/irq is written.
|
|
|
|
if(RxFlow) // Waiting x slot times before continuing so pause is deactivated.
|
|
repeat(64 * 2 * pause_value) @(posedge mrx_clk);
|
|
end
|
|
join
|
|
#1 check_rx_bd(127, data);
|
|
// Checking buffer descriptor
|
|
if(PassAll)
|
|
begin
|
|
if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
|
|
begin
|
|
$display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
|
|
begin
|
|
$display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// Checking if interrupt was generated
|
|
if(RxFlow || PassAll)
|
|
begin
|
|
if (!wb_int)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (wb_int)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(RxFlow)
|
|
begin
|
|
if(data !== (`ETH_INT_RXC))
|
|
begin
|
|
test_fail("RXC is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
else if(PassAll)
|
|
begin
|
|
if(data !== (`ETH_INT_RXB))
|
|
begin
|
|
test_fail("RXB is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 0)
|
|
begin
|
|
test_fail("No interrupt should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
|
|
end
|
|
end
|
|
end
|
|
// disable RX
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Receive control frames with PASSALL option turned on and ////
|
|
//// off. Using only one RX buffer decriptor ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 3) //
|
|
begin
|
|
// TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )
|
|
test_name = "TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )";
|
|
`TIME; $display(" TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )");
|
|
|
|
// unmask interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX_FLOW control
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// prepare one packet of 100 bytes long
|
|
// st_data = 8'h1A;
|
|
// set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
|
// append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
|
|
st_data = 8'h01;
|
|
set_tx_packet(`MEMORY_BASE + 64, 100, 8'h01); // length without CRC
|
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
|
|
set_tx_bd_wrap(0);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// write to phy's control register for 100Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 100;
|
|
|
|
// RXB and RXC interrupts masked
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
|
|
for (i=0; i<3; i=i+1)
|
|
begin
|
|
pause_value = i+2;
|
|
set_rx_control_packet(0, pause_value); // CRC already appended
|
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
|
case (i)
|
|
0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
|
|
begin
|
|
PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
|
|
begin
|
|
PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
|
|
begin
|
|
PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
default:
|
|
begin
|
|
`TIME; $display("*E We should never get here !!!");
|
|
test_fail("We should never get here !!!");
|
|
fail = fail + 1;
|
|
end
|
|
endcase
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
// set wrap bit and empty bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
// transmit
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
`TIME; $display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // received pause frame
|
|
repeat(5) @(posedge mrx_clk); // Wait some time so pause is activated.
|
|
repeat(5) @(posedge mtx_clk); // Wait some time so pause is activated.
|
|
set_tx_bd_ready(0, 0); // Request sending the data. Data should not be sent when pause frame was received
|
|
// and RxFlow enabled.
|
|
// When we exit the while loop, status frame is received
|
|
repeat(`ETH_TX_FIFO_DEPTH) @(eth_ma_wb_ack_i); // Waiting until TX fifo is filled.
|
|
repeat(10) @(posedge mtx_clk); // Wait some time for tx start.
|
|
end
|
|
join
|
|
#1 check_rx_bd(127, data);
|
|
// Checking buffer descriptor
|
|
if(PassAll)
|
|
begin
|
|
if(enable_irq_in_rxbd)
|
|
begin
|
|
if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
|
|
begin
|
|
`TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 32'h402100) // Rx BD must not be marked as EMPTY (control frame is received)
|
|
begin
|
|
`TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
|
|
begin
|
|
`TIME; $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// Checking if interrupt was generated
|
|
if (wb_int)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
|
|
test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
|
|
fail = fail + 1;
|
|
end
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(RxFlow)
|
|
begin
|
|
if(data !== (`ETH_INT_RXC))
|
|
begin
|
|
test_fail("RXC is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
else if(enable_irq_in_rxbd)
|
|
begin
|
|
if(data !== (`ETH_INT_RXB))
|
|
begin
|
|
test_fail("RXB is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 0)
|
|
begin
|
|
test_fail("Some IRQs is active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
end
|
|
if(RxFlow)
|
|
begin
|
|
if(MTxEn) // If pause frame was received OK, transmission of the data packet should not start
|
|
begin
|
|
`TIME; $display("*E Transmission should not be started because pause frame was received.");
|
|
test_fail("Transmission should not be started because pause frame was received.");
|
|
fail = fail + 1;
|
|
end
|
|
while(pause_value)
|
|
begin
|
|
pause_value=pause_value-1;
|
|
repeat(2*64) @(posedge mtx_clk); // Wait for the time needed for the pause (1 slot).
|
|
if((!pause_value) && (!MTxEn)) // Transmission should be enabled now.
|
|
begin
|
|
`TIME; $display("*E Transmission should be started because pause passed.");
|
|
test_fail("Transmission should be started because pause passed.");
|
|
fail = fail + 1;
|
|
end
|
|
else if((pause_value) && (MTxEn)) // Transmission should not be enabled now.
|
|
begin
|
|
`TIME; $display("*E Transmission should still be paused.");
|
|
test_fail("Transmission should still be paused.");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if(!MTxEn) // Pause frame was not received because RxFlow is turned off.
|
|
begin
|
|
`TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
|
|
test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
wait(wb_int); // Wait antil frame transmission is over and irq generated
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== (`ETH_INT_TXB))
|
|
begin
|
|
test_fail("TXB is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E TXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear TXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
// End: Test is irq is set while RXB and RXC interrupts are masked.
|
|
|
|
// Now all interrupts are unmasked. Performing tests again.
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
for (i=0; i<4; i=i+1)
|
|
begin
|
|
pause_value = i+1;
|
|
set_rx_control_packet(0, pause_value); // CRC already appended
|
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
|
case (i)
|
|
0: // PASSALL = 0, RXFLOW = 0
|
|
begin
|
|
PassAll=0; RxFlow=0;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
1: // PASSALL = 0, RXFLOW = 1
|
|
begin
|
|
PassAll=0; RxFlow=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
2: // PASSALL = 1, RXFLOW = 0
|
|
begin
|
|
PassAll=1; RxFlow=0;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
default: // 3: PASSALL = 1, RXFLOW = 1
|
|
begin
|
|
PassAll=1; RxFlow=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 1 and RXFLOW = 1
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
endcase
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
// set wrap bit and empty bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
// transmit
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin
|
|
#1 check_rx_bd(127, data);
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
$display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(50) @(posedge mrx_clk); // Wait some time so frame is received and
|
|
repeat (100) @(posedge wb_clk); // status/irq is written.
|
|
|
|
if(RxFlow) // Waiting x slot times before continuing so pause is deactivated.
|
|
repeat(64 * 2 * pause_value) @(posedge mrx_clk);
|
|
end
|
|
join
|
|
#1 check_rx_bd(127, data);
|
|
// Checking buffer descriptor
|
|
if(PassAll)
|
|
begin
|
|
if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
|
|
begin
|
|
`TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
|
|
begin
|
|
`TIME; $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// Checking if interrupt was generated
|
|
|
|
if(RxFlow | PassAll)
|
|
begin
|
|
if (!wb_int)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (wb_int)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(RxFlow)
|
|
begin
|
|
if(data !== (`ETH_INT_RXC))
|
|
begin
|
|
test_fail("RXC is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
else if(PassAll)
|
|
begin
|
|
if(data !== (`ETH_INT_RXB))
|
|
begin
|
|
test_fail("RXB is not set or multiple IRQs active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
else
|
|
begin
|
|
if(data !== 0)
|
begin
|
begin
|
|
test_fail("No interrupt should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
|
|
end
|
|
end
|
|
end
|
|
// disable RX
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test inserts control frames while transmitting normal ////
|
//// Random receive and transmit frames at one TX and ////
|
//// frames. Using 4 TX buffer decriptors ( 10Mbps ). ////
|
//// one RX buffer decriptor ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) //
|
if (test_num == 4) //
|
begin
|
begin
|
// TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )
|
// TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )
|
test_name = "TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )";
|
test_name = "TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )";
|
`TIME; $display(" TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )");
|
`TIME; $display(" TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )");
|
|
|
// reset MAC completely
|
// unmask interrupts
|
hard_reset;
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
// set wb slave response
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
// set 1 TX and 1 RX buffer descriptor (8'h01) - must be set before RX enable
|
max_tmp = 0;
|
wbm_write(`ETH_TX_BD_NUM, 32'h01, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
min_tmp = 0;
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// set 4 TX buffer descriptors - must be set before TX enable
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
// enable TX, set full-duplex mode, padding and CRC appending
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable TX flow control
|
// enable flow control
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// Set MAC address
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW | `ETH_CTRLMODER_TXFLOW,
|
mac_hi_addr = 32'h00000001;
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
mac_lo_addr = 32'h02030405;
|
// prepare one RX and one TX packet of 100 bytes long
|
wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
rx_len = 100; // length of frame without CRC
|
wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
st_data = 8'h1A;
|
// prepare two packets of MAXFL length
|
set_rx_packet(200, rx_len, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
append_rx_crc (200, rx_len, 1'b0, 1'b0); // CRC for data packet
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
tx_len = 64; // length of frame without CRC
|
min_tmp = tmp[31:16];
|
st_data = 8'h01;
|
st_data = 8'h34;
|
set_tx_packet(`MEMORY_BASE + 64, tx_len, st_data); // length without CRC
|
set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
|
// set TX and RX Buffer Descriptors
|
st_data = 8'h56;
|
tx_bd_num = 0; // tx BDs go from 0 to 0
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
|
rx_bd_num = 1; // rx BDs go from 1 to 1
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
|
// set EQUAL mrx_clk to mtx_clk!
|
|
// eth_phy.set_mrx_equal_mtx = 1'b1;
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 10;
|
|
|
frame_started = 0;
|
// TXB and RXB interrupts masked
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY | `ETH_INT_TXC | `ETH_INT_RXC,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
tmp_len = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
num_of_bd = 0;
|
num_of_rx_frames = 0;
|
i_length = 0; // 0;
|
// num_of_iter = 0;
|
// Initialize one part of memory with data of control packet
|
// TX frame loop & RX frame loop work independently
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
|
fork
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
|
// TX frame loop
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
|
while (num_of_frames < 400)
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
|
|
// append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0); // CRC is appended after the data
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame will be sent while no other transmission is in progress.//
|
|
// TXC interrupt won't be unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
begin
|
test_fail("IRQ already pending!");
|
eth_phy.set_tx_mem_addr(64 + num_of_frames);
|
fail = fail + 1;
|
// set tx bd
|
`TIME; $display("*E IRQ already pending!");
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
end
|
end
|
if (wb_int)
|
set_tx_bd(0, 0, tx_len, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
|
|
set_tx_bd_wrap(0);
|
|
set_tx_bd_ready(0, 0);
|
|
check_tx_bd(0, data);
|
|
// check frame
|
|
i = 0;
|
|
while((i < 100) && (MTxEn === 1'b0)) // wait for start of TX frame!
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
@(posedge mtx_clk);
|
fail = fail + 1;
|
i = i + 1;
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
// first destination address on ethernet PHY
|
if (MTxEn != 1'b1)
|
eth_phy.set_tx_mem_addr(0);
|
|
// Request sending the control frame with pause value = 0x1111
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait for transmission to come over
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time
|
|
// check interrupt
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
begin
|
test_fail("TXC IRQ should be set!");
|
`TIME; $display("*E Tx Frame %0d: MAC TX didn't start transmitting the packet", num_of_frames);
|
|
test_fail("MAC TX didn't start transmitting the packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXC IRQ should be set!");
|
#10000 $stop;
|
end
|
end
|
if (wb_int)
|
|
|
repeat (30) @(posedge mtx_clk); // waiting some time so PHY clears the tx_len
|
|
|
|
wait ((MTxEn === 1'b0) || (eth_phy.tx_len > (tx_len + 4))) // wait for end of TX frame
|
|
if (MTxEn != 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set because TXC irq is masked!");
|
`TIME; $display("*E Tx Frame %0d: MAC TX didn't stop transmitting the packet", num_of_frames);
|
|
test_fail("MAC TX didn't stop transmitting the packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
|
#10000 $stop;
|
end
|
end
|
// Clear TXC interrupt
|
tmp_len = eth_phy.tx_len;
|
wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// wait for WB master if it is working
|
if (wb_int)
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
@(posedge wb_clk);
|
|
end
|
|
check_tx_bd(0, data);
|
|
while (data[15] === 1)
|
|
begin
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
end
|
|
check_tx_bd(0, data);
|
|
end
|
|
repeat (1) @(posedge wb_clk);
|
|
// check length of a PACKET
|
|
if (tmp_len != (tx_len + 4))
|
|
begin
|
|
`TIME; $display("*E Tx Frame %0d: Wrong length of the packet out from MAC (%0d instead of %0d)", num_of_frames,
|
|
tmp_len, (tx_len + 4));
|
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
// check transmited TX packet
|
// check transmitted TX packet data
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
check_tx_packet((`MEMORY_BASE + 64), (64 + num_of_frames), (tx_len), tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
$display("Wrong data of the transmitted packet");
|
`TIME; $display("*E Tx Frame %0d: Wrong data of the transmitted packet", num_of_frames);
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
check_tx_crc((64 + num_of_frames), (tx_len), 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
$display("Wrong CRC of the transmitted packet");
|
`TIME; $display("*E Tx Frame %0d: Wrong CRC of the transmitted packet", num_of_frames);
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
// check WB INT signal
|
// In the following section, control frame will be sent while no other transmission is in progress.//
|
if (wb_int !== 1'b0)
|
// TXC interrupt is unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// unmask all interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
begin
|
test_fail("IRQ already pending!");
|
`TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
|
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E IRQ already pending!");
|
|
end
|
end
|
if (wb_int)
|
// check TX buffer descriptor of a packet
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
end
|
|
check_tx_bd(0, data);
|
|
if (data[15:0] !== 16'h7800)
|
|
begin
|
|
`TIME; $display("*E Tx Frame %0d: TX buffer descriptor status is not correct: %0h", num_of_frames, data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
@(posedge wb_clk);
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
// unmask only TXC interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// Request sending the control frame with pause value = 0x2222
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF); // Just for data test
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait for transmit to come over
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time
|
|
// check INT
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if(data !== `ETH_INT_TXC)
|
if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
|
begin
|
begin
|
test_fail("TXC IRQ should be set!");
|
`TIME; $display("*E Tx Frame %0d: Interrupt Transmit Buffer was not set, interrupt reg: %0h", num_of_frames, data);
|
|
test_fail("Interrupt Transmit Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
end
|
end
|
if (!wb_int)
|
if ((data & (~(`ETH_INT_TXB | `ETH_INT_RXB))) !== 0) // RXB might occur at the same time - not error
|
begin
|
begin
|
test_fail("WB INT signal should be set!");
|
`TIME; $display("*E Tx Frame %0d: Other interrupts (except Tx and Rx Buffer) were set, interrupt reg: %0h",
|
|
num_of_frames, data);
|
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should be set!");
|
|
end
|
end
|
// Clear TXC interrupt
|
// clear interrupts (except RXB)
|
wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// wait for WB master if it is working
|
if (wb_int)
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
@(posedge wb_clk);
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
// check transmited TX packet
|
wbm_write(`ETH_INT, (data & (~`ETH_INT_RXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
// check WB INT signal
|
if (tmp > 0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
$display("Wrong data of the transmitted packet");
|
`TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// Displays
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
if (num_of_frames[2:0] == 3'b111)
|
if (tmp > 0)
|
|
begin
|
begin
|
$display("Wrong CRC of the transmitted packet");
|
$display(" ->8 frames transmitted");
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
end
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
// set length (loop variable)
|
// In the following section, control frame sending is requested while no other transmission //
|
num_of_frames = num_of_frames + 1;
|
// is in progress. TXC interrupt is unmasked. //
|
end // TX frame loop
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
// RX frame loop
|
// unmask all interrupts
|
while (num_of_rx_frames < 400)
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
begin
|
test_fail("IRQ already pending!");
|
// set rx bd
|
fail = fail + 1;
|
// wait for WB master if it is working
|
`TIME; $display("*E IRQ already pending!");
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
#1;
|
end
|
end
|
if (wb_int)
|
set_rx_bd(1, 1, 1'b1, (`MEMORY_BASE + 200 + num_of_rx_frames));
|
|
set_rx_bd_wrap(1);
|
|
set_rx_bd_empty(1, 1);
|
|
// check frame
|
|
fork
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 200, (rx_len + 4), 1'b0);
|
fail = fail + 1;
|
repeat(10) @(posedge mrx_clk);
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame request and data send request are both set. At the //
|
|
// beginning control frame request will be faster than data send request, later the opposite. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
for (i=0; i<32; i=i+1)
|
|
begin
|
begin
|
// Request sending the control frame with pause value = 0x5678
|
wait (MRxDV === 1'b1); // start receive
|
set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
|
// wait for WB master if it is working
|
set_tx_bd_wrap(0);
|
@(posedge wb_clk);
|
// first destination address on ethernet PHY
|
#1;
|
eth_phy.set_tx_mem_addr(0);
|
while (wbm_working)
|
set_tx_bd_ready(0, 0);
|
|
// wait for transmission to start
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
repeat(i) @ (posedge mtx_clk); // We need to wait some time until TX module starts using the data (preamble stage is over)
|
|
// Send control frame request
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF); // Just for data test
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait until transmission is over
|
|
wait (MTxEn === 1'b0); // Wait until data frame transmission is over
|
|
repeat(10) @ (posedge mtx_clk); // wait some time so status is written
|
|
tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
|
|
repeat(10) @ (posedge wb_clk); // wait some time so status is written
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// check interrupt depending on which packet was sent
|
|
if(tmp_len == 64) // Control frame
|
|
begin
|
begin
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
@(posedge wb_clk);
|
if(data !== `ETH_INT_TXC)
|
#1;
|
|
end
|
|
check_rx_bd(1, data);
|
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("TXC IRQ should be set!");
|
`TIME; $display("*E Rx Frame %0d: Wrong buffer descriptor's ready bit read out from MAC", num_of_rx_frames);
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
`TIME; $display("ETH_INT = 0x%0x", data);
|
|
end
|
end
|
|
wait (MRxDV === 1'b0); // end receive
|
|
|
|
while (data[15] === 1)
|
|
begin
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
#1;
|
|
end
|
|
check_rx_bd(1, data);
|
end
|
end
|
else
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
join
|
|
// check length of a PACKET
|
|
|
|
// Additional read because simulator was not working OK.
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
begin
|
begin
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
@(posedge wb_clk);
|
if(data !== `ETH_INT_TXB)
|
#1;
|
|
end
|
|
check_rx_bd(1, data);
|
|
|
|
if (data[31:16] != (rx_len + 4))
|
begin
|
begin
|
test_fail("TXB IRQ should be set!");
|
`TIME; $display("*E Rx Frame %0d: Wrong length of the packet written to MAC's register (%0d instead of %0d)",
|
|
num_of_rx_frames, data[31:16], (rx_len + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXB IRQ should be set!");
|
|
`TIME; $display("ETH_INT = 0x%0x", data);
|
|
end
|
end
|
end
|
// check received RX packet data and CRC
|
// check transmited TX packet
|
check_rx_packet(200, (`MEMORY_BASE + 200 + num_of_rx_frames), (rx_len + 4), 1'b0, 1'b0, tmp);
|
if(tmp_len == 64) // Control frame
|
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
else
|
|
check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
|
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
$display("Wrong data of the transmitted packet");
|
`TIME; $display("*E Rx Frame %0d: Wrong data of the received packet", num_of_rx_frames);
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check WB INT signal
|
if(tmp_len == 64) // Control frame
|
if (wb_int !== 1'b0)
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
else
|
|
#1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
|
|
|
|
if (tmp > 0)
|
|
begin
|
begin
|
$display("Wrong CRC of the transmitted packet");
|
`TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// check RX buffer descriptor of a packet
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
#1;
|
|
end
|
|
check_rx_bd(1, data);
|
|
if (data[15:0] !== 16'h6080)
|
|
begin
|
|
`TIME; $display("*E Rx Frame %0d: RX buffer descriptor status is not correct: %0h", num_of_rx_frames, data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// wait for control frame to transmit
|
|
wait (MTxEn === 1'b1); // start transmit of the control frame
|
|
wait (MTxEn === 1'b0); // end transmit of the control frame
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time so status is written
|
|
// check interrupts
|
// check interrupts
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
#1;
|
|
end
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
|
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
test_fail("TXC and TXB IRQ should be set!");
|
`TIME; $display("*E Rx Frame %0d: Interrupt Receive Buffer was not set, interrupt reg: %0h",
|
|
num_of_rx_frames, data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
|
|
end
|
end
|
if (!wb_int)
|
if ((data & (~(`ETH_INT_RXB | `ETH_INT_TXB))) !== 0) // TXB might occur at the same time - not error
|
begin
|
begin
|
test_fail("WB INT signal should be set!");
|
`TIME; $display("*E Rx Frame %0d: Other interrupts (except Rx and Tx Buffer) were set, interrupt reg: %0h",
|
|
num_of_rx_frames, data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should be set!");
|
|
end
|
end
|
// Clear TXC and TXB interrupt
|
// clear interrupts (except TXB)
|
wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
|
// wait for WB master if it is working
|
if (wb_int)
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
@(posedge wb_clk);
|
fail = fail + 1;
|
#1;
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
if(tmp_len == 64) // Control frame
|
wbm_write(`ETH_INT, (data & (~`ETH_INT_TXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
|
// check WB INT signal
|
else
|
if (wb_int !== 1'b0)
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
if (tmp > 0)
|
|
begin
|
begin
|
$display("Wrong data of the transmitted packet");
|
`TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// Displays
|
if(tmp_len == 64) // Control frame
|
if (num_of_rx_frames[2:0] == 3'b111)
|
#1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
|
|
else
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
|
begin
|
begin
|
$display("Wrong CRC of the transmitted packet");
|
$display(" ->8 frames received");
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
end
|
end // for loop
|
// set length (loop variable)
|
|
num_of_rx_frames = num_of_rx_frames + 1;
|
|
end // RX frame loop
|
|
join
|
|
// disable TX & RX
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_PAD | `ETH_MODER_CRCEN |
|
|
`ETH_MODER_IFG | `ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set DIFFERENT mrx_clk to mtx_clk!
|
|
// eth_phy.set_mrx_equal_mtx = 1'b0;
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test inserts control frames while transmitting normal ////
|
//// Random receive and transmit frames at one TX and ////
|
//// frames. Using 4 TX buffer decriptors ( 100Mbps ). ////
|
//// one RX buffer decriptor ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) //
|
if (test_num == 5) //
|
begin
|
begin
|
// TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )
|
// TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps )
|
test_name = "TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )";
|
test_name = "TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps )";
|
`TIME; $display(" TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )");
|
`TIME; $display(" TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps )");
|
|
|
// reset MAC completely
|
// unmask interrupts
|
hard_reset;
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
// set wb slave response
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
// set 1 TX and 1 RX buffer descriptor (8'h01) - must be set before RX enable
|
max_tmp = 0;
|
wbm_write(`ETH_TX_BD_NUM, 32'h01, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
min_tmp = 0;
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// set 4 TX buffer descriptors - must be set before TX enable
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
// enable TX, set full-duplex mode, padding and CRC appending
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable TX flow control
|
// enable flow control
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// Set MAC address
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW | `ETH_CTRLMODER_TXFLOW,
|
mac_hi_addr = 32'h00000001;
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
mac_lo_addr = 32'h02030405;
|
// prepare one RX and one TX packet of 100 bytes long
|
wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
rx_len = 100; // length of frame without CRC
|
wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
st_data = 8'h1A;
|
// prepare two packets of MAXFL length
|
set_rx_packet(200, rx_len, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
append_rx_crc (200, rx_len, 1'b0, 1'b0); // CRC for data packet
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
tx_len = 64; // length of frame without CRC
|
min_tmp = tmp[31:16];
|
st_data = 8'h01;
|
st_data = 8'h34;
|
set_tx_packet(`MEMORY_BASE + 64, tx_len, st_data); // length without CRC
|
set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
|
// set TX and RX Buffer Descriptors
|
st_data = 8'h56;
|
tx_bd_num = 0; // tx BDs go from 0 to 0
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
|
rx_bd_num = 1; // rx BDs go from 1 to 1
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
|
// set EQUAL mrx_clk to mtx_clk!
|
|
// eth_phy.set_mrx_equal_mtx = 1'b1;
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 100;
|
|
|
frame_started = 0;
|
// TXB and RXB interrupts masked
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY | `ETH_INT_TXC | `ETH_INT_RXC,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
tmp_len = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
num_of_bd = 0;
|
num_of_rx_frames = 0;
|
i_length = 0; // 0;
|
// num_of_iter = 0;
|
// Initialize one part of memory with data of control packet
|
// TX frame loop & RX frame loop work independently
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
|
fork
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
|
// TX frame loop
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
|
while (num_of_frames < 400)
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
|
|
// append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0); // CRC is appended after the data
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame will be sent while no other transmission is in progress.//
|
|
// TXC interrupt won't be unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
begin
|
test_fail("IRQ already pending!");
|
eth_phy.set_tx_mem_addr(64 + num_of_frames);
|
fail = fail + 1;
|
// set tx bd
|
`TIME; $display("*E IRQ already pending!");
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
end
|
end
|
if (wb_int)
|
set_tx_bd(0, 0, tx_len, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
|
|
set_tx_bd_wrap(0);
|
|
set_tx_bd_ready(0, 0);
|
|
check_tx_bd(0, data);
|
|
// check frame
|
|
i = 0;
|
|
while((i < 100) && (MTxEn === 1'b0)) // wait for start of TX frame!
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
@(posedge mtx_clk);
|
fail = fail + 1;
|
i = i + 1;
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
// first destination address on ethernet PHY
|
if (MTxEn != 1'b1)
|
eth_phy.set_tx_mem_addr(0);
|
|
// Request sending the control frame with pause value = 0x1111
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait for transmission to come over
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time
|
|
// check interrupt
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
begin
|
test_fail("TXC IRQ should be set!");
|
`TIME; $display("*E Tx Frame %0d: MAC TX didn't start transmitting the packet", num_of_frames);
|
|
test_fail("MAC TX didn't start transmitting the packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXC IRQ should be set!");
|
#10000 $stop;
|
end
|
end
|
if (wb_int)
|
|
|
repeat (30) @(posedge mtx_clk); // waiting some time so PHY clears the tx_len
|
|
|
|
wait ((MTxEn === 1'b0) || (eth_phy.tx_len > (tx_len + 4))) // wait for end of TX frame
|
|
if (MTxEn != 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set because TXC irq is masked!");
|
`TIME; $display("*E Tx Frame %0d: MAC TX didn't stop transmitting the packet", num_of_frames);
|
|
test_fail("MAC TX didn't stop transmitting the packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
|
#10000 $stop;
|
end
|
end
|
// Clear TXC interrupt
|
tmp_len = eth_phy.tx_len;
|
wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// wait for WB master if it is working
|
if (wb_int)
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
@(posedge wb_clk);
|
|
end
|
|
check_tx_bd(0, data);
|
|
while (data[15] === 1)
|
|
begin
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
end
|
|
check_tx_bd(0, data);
|
|
end
|
|
repeat (1) @(posedge wb_clk);
|
|
// check length of a PACKET
|
|
if (tmp_len != (tx_len + 4))
|
|
begin
|
|
`TIME; $display("*E Tx Frame %0d: Wrong length of the packet out from MAC (%0d instead of %0d)", num_of_frames,
|
|
tmp_len, (tx_len + 4));
|
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
// check transmited TX packet
|
// check transmitted TX packet data
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
check_tx_packet((`MEMORY_BASE + 64), (64 + num_of_frames), (tx_len), tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
$display("Wrong data of the transmitted packet");
|
`TIME; $display("*E Tx Frame %0d: Wrong data of the transmitted packet", num_of_frames);
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
check_tx_crc((64 + num_of_frames), (tx_len), 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
$display("Wrong CRC of the transmitted packet");
|
`TIME; $display("*E Tx Frame %0d: Wrong CRC of the transmitted packet", num_of_frames);
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
|
end
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// check TX buffer descriptor of a packet
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
end
|
|
check_tx_bd(0, data);
|
|
if (data[15:0] !== 16'h7800)
|
|
begin
|
|
`TIME; $display("*E Tx Frame %0d: TX buffer descriptor status is not correct: %0h", num_of_frames, data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
end
|
end
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame will be sent while no other transmission is in progress.//
|
|
// TXC interrupt is unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// unmask all interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if(data)
|
if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
|
begin
|
begin
|
test_fail("IRQ already pending!");
|
`TIME; $display("*E Tx Frame %0d: Interrupt Transmit Buffer was not set, interrupt reg: %0h", num_of_frames, data);
|
|
test_fail("Interrupt Transmit Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E IRQ already pending!");
|
|
end
|
end
|
if (wb_int)
|
if ((data & (~(`ETH_INT_TXB | `ETH_INT_RXB))) !== 0) // RXB might occur at the same time - not error
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
`TIME; $display("*E Tx Frame %0d: Other interrupts (except Tx and Rx Buffer) were set, interrupt reg: %0h",
|
|
num_of_frames, data);
|
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
// unmask only TXC interrupts
|
// clear interrupts (except RXB)
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// wait for WB master if it is working
|
// first destination address on ethernet PHY
|
@(posedge wb_clk);
|
eth_phy.set_tx_mem_addr(0);
|
while (wbm_working)
|
// Request sending the control frame with pause value = 0x2222
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF); // Just for data test
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait for transmit to come over
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
repeat(10) @ (posedge wb_clk); // wait some time
|
|
repeat(10) @ (posedge mtx_clk); // wait some time
|
|
// check INT
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== `ETH_INT_TXC)
|
|
begin
|
begin
|
test_fail("TXC IRQ should be set!");
|
@(posedge wb_clk);
|
fail = fail + 1;
|
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
end
|
end
|
if (!wb_int)
|
wbm_write(`ETH_INT, (data & (~`ETH_INT_RXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should be set!");
|
`TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
|
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should be set!");
|
|
end
|
end
|
// Clear TXC interrupt
|
// Displays
|
wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (num_of_frames[2:0] == 3'b111)
|
if (wb_int)
|
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
$display(" ->8 frames transmitted");
|
fail = fail + 1;
|
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
// check transmited TX packet
|
// set length (loop variable)
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
num_of_frames = num_of_frames + 1;
|
if (tmp > 0)
|
end // TX frame loop
|
|
// RX frame loop
|
|
while (num_of_rx_frames < 400)
|
begin
|
begin
|
$display("Wrong data of the transmitted packet");
|
// set rx bd
|
test_fail("Wrong data of the transmitted packet");
|
// wait for WB master if it is working
|
fail = fail + 1;
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
#1;
|
end
|
end
|
// check transmited TX packet CRC
|
set_rx_bd(1, 1, 1'b1, (`MEMORY_BASE + 200 + num_of_rx_frames));
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
set_rx_bd_wrap(1);
|
if (tmp > 0)
|
set_rx_bd_empty(1, 1);
|
|
// check frame
|
|
fork
|
begin
|
begin
|
$display("Wrong CRC of the transmitted packet");
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 200, (rx_len + 4), 1'b0);
|
test_fail("Wrong CRC of the transmitted packet");
|
repeat(10) @(posedge mrx_clk);
|
fail = fail + 1;
|
|
end
|
end
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// In the following section, control frame sending is requested while no other transmission //
|
|
// is in progress. TXC interrupt is unmasked. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// unmask all interrupts
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data)
|
|
begin
|
begin
|
test_fail("IRQ already pending!");
|
wait (MRxDV === 1'b1); // start receive
|
fail = fail + 1;
|
// wait for WB master if it is working
|
`TIME; $display("*E IRQ already pending!");
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
#1;
|
end
|
end
|
if (wb_int)
|
check_rx_bd(1, data);
|
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
`TIME; $display("*E Rx Frame %0d: Wrong buffer descriptor's ready bit read out from MAC", num_of_rx_frames);
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
|
wait (MRxDV === 1'b0); // end receive
|
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
while (data[15] === 1)
|
// In the following section, control frame request and data send request are both set. At the //
|
|
// beginning control frame request will be faster than data send request, later the opposite. //
|
|
/////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
for (i=0; i<32; i=i+1)
|
|
begin
|
|
// Request sending the control frame with pause value = 0x5678
|
|
set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
|
|
set_tx_bd_wrap(0);
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
set_tx_bd_ready(0, 0);
|
|
// wait for transmission to start
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
repeat(i) @ (posedge mtx_clk); // We need to wait some time until TX module starts using the data (preamble stage is over)
|
|
// Send control frame request
|
|
wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF); // Just for data test
|
|
wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// wait until transmission is over
|
|
wait (MTxEn === 1'b0); // Wait until data frame transmission is over
|
|
repeat(10) @ (posedge mtx_clk); // wait some time so status is written
|
|
tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
|
|
repeat(10) @ (posedge wb_clk); // wait some time so status is written
|
|
// first destination address on ethernet PHY
|
|
eth_phy.set_tx_mem_addr(0);
|
|
// check interrupt depending on which packet was sent
|
|
|
|
if(tmp_len == 64) // Control frame
|
|
begin
|
begin
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// wait for WB master if it is working
|
if(data !== `ETH_INT_TXC)
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
begin
|
begin
|
test_fail("TXC IRQ should be set!");
|
@(posedge wb_clk);
|
fail = fail + 1;
|
#1;
|
`TIME; $display("*E TXC IRQ should be set!");
|
|
`TIME; $display("ETH_INT = 0x%0x", data);
|
|
end
|
end
|
|
check_rx_bd(1, data);
|
end
|
end
|
else
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
join
|
|
// check length of a PACKET
|
|
|
|
// Additional read because simulator was not working OK.
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
begin
|
begin
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
@(posedge wb_clk);
|
if(data !== `ETH_INT_TXB)
|
#1;
|
|
end
|
|
check_rx_bd(1, data);
|
|
|
|
if (data[31:16] != (rx_len + 4))
|
begin
|
begin
|
test_fail("TXB IRQ should be set!");
|
`TIME; $display("*E Rx Frame %0d: Wrong length of the packet written to MAC's register (%0d instead of %0d)",
|
|
num_of_rx_frames, data[31:16], (rx_len + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXB IRQ should be set!");
|
|
`TIME; $display("ETH_INT = 0x%0x", data);
|
|
end
|
|
end
|
end
|
// check transmited TX packet
|
// check received RX packet data and CRC
|
if(tmp_len == 64) // Control frame
|
check_rx_packet(200, (`MEMORY_BASE + 200 + num_of_rx_frames), (rx_len + 4), 1'b0, 1'b0, tmp);
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
|
else
|
|
check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
|
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
$display("Wrong data of the transmitted packet");
|
`TIME; $display("*E Rx Frame %0d: Wrong data of the received packet", num_of_rx_frames);
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check WB INT signal
|
if(tmp_len == 64) // Control frame
|
if (wb_int !== 1'b0)
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
else
|
|
#1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
|
|
|
|
if (tmp > 0)
|
|
begin
|
begin
|
$display("Wrong CRC of the transmitted packet");
|
`TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// wait for control frame to transmit
|
// check RX buffer descriptor of a packet
|
wait (MTxEn === 1'b1); // start transmit of the control frame
|
// wait for WB master if it is working
|
wait (MTxEn === 1'b0); // end transmit of the control frame
|
@(posedge wb_clk);
|
repeat(10) @ (posedge wb_clk); // wait some time
|
#1;
|
repeat(10) @ (posedge mtx_clk); // wait some time so status is written
|
while (wbm_working)
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
|
|
begin
|
begin
|
test_fail("TXC and TXB IRQ should be set!");
|
@(posedge wb_clk);
|
|
#1;
|
|
end
|
|
check_rx_bd(1, data);
|
|
if (data[15:0] !== 16'h6080)
|
|
begin
|
|
`TIME; $display("*E Rx Frame %0d: RX buffer descriptor status is not correct: %0h", num_of_rx_frames, data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
|
|
end
|
end
|
if (!wb_int)
|
// check interrupts
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
begin
|
begin
|
test_fail("WB INT signal should be set!");
|
@(posedge wb_clk);
|
|
#1;
|
|
end
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Rx Frame %0d: Interrupt Receive Buffer was not set, interrupt reg: %0h",
|
|
num_of_rx_frames, data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should be set!");
|
|
end
|
end
|
// Clear TXC and TXB interrupt
|
if ((data & (~(`ETH_INT_RXB | `ETH_INT_TXB))) !== 0) // TXB might occur at the same time - not error
|
wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
|
|
if (wb_int)
|
|
begin
|
begin
|
test_fail("WB INT signal should not be set!");
|
`TIME; $display("*E Rx Frame %0d: Other interrupts (except Rx and Tx Buffer) were set, interrupt reg: %0h",
|
|
num_of_rx_frames, data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E WB INT signal should not be set!");
|
|
end
|
end
|
if(tmp_len == 64) // Control frame
|
// clear interrupts (except TXB)
|
check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
|
// wait for WB master if it is working
|
else
|
@(posedge wb_clk);
|
check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
|
#1;
|
if (tmp > 0)
|
while (wbm_working)
|
begin
|
begin
|
$display("Wrong data of the transmitted packet");
|
@(posedge wb_clk);
|
test_fail("Wrong data of the transmitted packet");
|
#1;
|
fail = fail + 1;
|
|
end
|
end
|
// check transmited TX packet CRC
|
wbm_write(`ETH_INT, (data & (~`ETH_INT_TXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if(tmp_len == 64) // Control frame
|
// check WB INT signal
|
#1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
|
if (wb_int !== 1'b0)
|
else
|
|
#1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
|
begin
|
begin
|
$display("Wrong CRC of the transmitted packet");
|
`TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end // for loop
|
// Displays
|
|
if (num_of_rx_frames[2:0] == 3'b111)
|
|
begin
|
|
$display(" ->8 frames received");
|
|
end
|
|
// set length (loop variable)
|
|
num_of_rx_frames = num_of_rx_frames + 1;
|
|
end // RX frame loop
|
|
join
|
|
// disable TX & RX
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_PAD | `ETH_MODER_CRCEN |
|
|
`ETH_MODER_IFG | `ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set DIFFERENT mrx_clk to mtx_clk!
|
|
// eth_phy.set_mrx_equal_mtx = 1'b0;
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
|
|
end
|
|
endtask // test_mac_full_duplex_flow_control
|
|
|
|
|
|
task test_mac_half_duplex_flow;
|
|
input [31:0] start_task;
|
|
input [31:0] end_task;
|
|
integer bit_start_1;
|
|
integer bit_end_1;
|
|
integer bit_start_2;
|
|
integer bit_end_2;
|
|
integer num_of_reg;
|
|
integer num_of_frames;
|
|
integer num_of_bd;
|
|
integer num_of_iter;
|
|
integer i_addr;
|
|
integer i_data;
|
|
integer i_length;
|
|
integer tmp_len;
|
|
integer tmp_bd;
|
|
integer tmp_bd_num;
|
|
integer tmp_data;
|
|
integer tmp_ipgt;
|
|
integer test_num;
|
|
reg [31:0] tx_bd_num;
|
|
reg [31:0] rx_bd_num;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
|
|
integer i;
|
|
integer i1;
|
|
integer i2;
|
|
integer i3;
|
|
integer ipgr1;
|
|
integer ipgr2;
|
|
reg coll;
|
|
integer fail;
|
|
integer speed;
|
|
integer mac_hi_addr;
|
|
integer mac_lo_addr;
|
|
reg frame_started;
|
|
reg frame_ended;
|
|
reg check_rx_frame;
|
|
reg check_tx_frame;
|
|
reg wait_for_tx_frame;
|
|
reg [31:0] addr;
|
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reg [31:0] data;
|
|
reg [31:0] tmp;
|
|
reg [ 7:0] st_data;
|
|
reg [15:0] max_tmp;
|
|
reg [15:0] min_tmp;
|
|
begin
|
|
// MAC HALF DUPLEX FLOW TEST
|
|
test_heading("MAC HALF DUPLEX FLOW TEST");
|
|
$display(" ");
|
|
$display("MAC HALF DUPLEX FLOW TEST");
|
|
fail = 0;
|
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
/*
|
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
|
-------------------------------------------------------------------------------------
|
|
set_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
|
|
set_tx_bd_wrap
|
|
(tx_bd_num_end[6:0]);
|
|
set_tx_bd_ready
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
check_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_status[31:0]);
|
|
clear_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and control RX buffer descriptors:
|
|
------------------------------------------------
|
|
set_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
|
|
set_rx_bd_wrap
|
|
(rx_bd_num_end[6:0]);
|
|
set_rx_bd_empty
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
check_rx_bd
|
|
(rx_bd_num_end[6:0], rx_bd_status);
|
|
clear_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and check TX packets:
|
|
-----------------------------------
|
|
set_tx_packet
|
|
(txpnt[31:0], len[15:0], eth_start_data[7:0]);
|
|
check_tx_packet
|
|
(txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
|
|
|
|
TASKS for set and check RX packets:
|
|
-----------------------------------
|
|
set_rx_packet
|
|
(rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
|
|
check_rx_packet
|
|
(rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
|
|
|
|
TASKS for append and check CRC to/of TX packet:
|
|
-----------------------------------------------
|
|
append_tx_crc
|
|
(txpnt_wb[31:0], len[15:0], negated_crc);
|
|
check_tx_crc
|
|
(txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
|
|
|
|
TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
|
|
--------------------------------------------------------------------------------
|
|
append_rx_crc
|
|
(rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
|
|
*/
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// test_mac_half_duplex_flow: ////
|
|
//// ////
|
|
//// 0: Test ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
|
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
|
begin
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Receive control frames with PASSALL option turned on and ////
|
//// Test defer and collision with IPGR2 while transmitting ////
|
//// off. Using only one RX buffer decriptor ( 10Mbps ). ////
|
//// and receiving normal frames. Using 4 TX and RX buffer ////
|
|
//// decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) //
|
if (test_num == 0) //
|
begin
|
begin
|
// TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )
|
// TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )
|
test_name = "TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )";
|
//
|
`TIME; $display(" TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )");
|
test_name = "TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )";
|
|
`TIME; $display(" TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )");
|
|
|
// unmask interrupts
|
// reset MAC completely
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
hard_reset;
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set wb slave response
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
max_tmp = 0;
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
min_tmp = 0;
|
|
// set 4 TX buffer descriptors (4 TX and 4 RX BDs will be used) - must be set before TX/RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable TX and RX, set half-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_RXEN | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX_FLOW control
|
// prepare two packets for TX and RX
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wait (wbm_working == 0);
|
// prepare one packet of 100 bytes long
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// st_data = 8'h1A;
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
// set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
min_tmp = tmp[31:16];
|
// append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
|
st_data = 8'h17;
|
st_data = 8'h01;
|
set_rx_packet(0, (min_tmp), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_tx_packet(`MEMORY_BASE + 64, 100, 8'h01); // length without CRC
|
append_rx_crc (0, (min_tmp), 1'b0, 1'b0);
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
|
st_data = 8'h92;
|
set_tx_bd_wrap(0);
|
set_tx_packet(`MEMORY_BASE, (min_tmp), st_data); // length without CRC
|
|
append_tx_crc (`MEMORY_BASE, (min_tmp), 1'b0);
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h0_00; // bit 6 reset - (10/100), bit 8 set - HD
|
speed = 10;
|
speed = 10;
|
|
|
// RXB and RXC interrupts masked
|
// set TX and RX Buffer Descriptors
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
|
tx_bd_num = 0; // tx BDs go from 0 to 3
|
`ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
rx_bd_num = 4; // rx BDs go from 4 to 7
|
// Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
|
ipgr2 = 0;
|
for (i=0; i<3; i=i+1)
|
i_length = min_tmp + 4;
|
begin
|
set_tx_bd(0, 3, i_length[15:0], 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
pause_value = i+2;
|
set_tx_bd_wrap(3);
|
set_rx_control_packet(0, pause_value); // CRC already appended
|
set_rx_bd(4, 7, 1'b1, `MEMORY_BASE);
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
set_rx_bd_wrap(7);
|
case (i)
|
set_rx_bd_empty(4, 7);
|
0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(10) @(posedge wb_clk);
|
|
|
|
num_of_frames = 0;// 0; // 10;
|
|
while (num_of_frames <= 35)
|
begin
|
begin
|
PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
|
st_data = 8'h2 + num_of_frames;
|
// enable interrupt generation
|
set_rx_packet(0, (min_tmp), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
append_rx_crc (0, (min_tmp), 1'b0, 1'b0);
|
// Set PASSALL = 0 and RXFLOW = 0
|
eth_phy.set_tx_mem_addr(num_of_frames);
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// CHECK END OF RECEIVE WHILE TRANSMITTING
|
end
|
if (num_of_frames == 0)
|
1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
|
|
begin
|
begin
|
PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
|
ipgr2 = 7'h0;
|
// enable interrupt generation
|
wait (wbm_working == 0);
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
wbm_write(`ETH_IPGR2, ipgr2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
end
|
2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
|
if (num_of_frames == 1)
|
begin
|
begin
|
PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
|
ipgr2 = 7'h1;
|
// enable interrupt generation
|
wait (wbm_working == 0);
|
set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
|
wbm_write(`ETH_IPGR2, ipgr2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
end
|
default:
|
if (num_of_frames == 2)
|
begin
|
begin
|
$display("*E We should never get here !!!");
|
ipgr2 = 7'h12;
|
test_fail("We should never get here !!!");
|
wait (wbm_working == 0);
|
fail = fail + 1;
|
wbm_write(`ETH_IPGR2, ipgr2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
endcase
|
frame_ended = 0;
|
// not detect carrier sense in FD and no collision
|
check_rx_frame = 0;
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
check_tx_frame = 0;
|
eth_phy.collision(0);
|
i = 0;
|
// set wrap bit and empty bit
|
coll = 0;
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
// transmit
|
|
fork
|
fork
|
begin
|
// send frames
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
begin // start with RX frame
|
|
repeat(num_of_frames) @(posedge mrx_clk);
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, i_length, 1'b0);
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
end
|
end
|
begin
|
begin // start with TX frame
|
wait (MRxDV === 1'b1); // start transmit
|
repeat(4) @(posedge mrx_clk);
|
#1 check_rx_bd(127, data);
|
repeat(2) @(posedge wb_clk);
|
if (data[15] !== 1)
|
#1 set_tx_bd_ready(tx_bd_num, tx_bd_num);
|
begin
|
|
$display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // received pause frame
|
|
repeat(5) @(posedge mrx_clk); // Wait some time so pause is activated.
|
|
repeat(5) @(posedge mtx_clk); // Wait some time so pause is activated.
|
|
set_tx_bd_ready(0, 0); // Request sending the data. Data should not be sent when pause frame was received
|
|
// and RxFlow enabled.
|
|
// When we exit the while loop, status frame is received
|
|
repeat(`ETH_TX_FIFO_DEPTH) @(eth_ma_wb_ack_i); // Waiting until TX fifo is filled.
|
|
repeat(10) @(posedge mtx_clk); // Wait some time for tx start.
|
|
end
|
end
|
join
|
// observe TX Enable, Carrier Sense and Collision - TX frame is not repeated after Late Collision
|
#1 check_rx_bd(127, data);
|
begin: collision0
|
// Checking buffer descriptor
|
wait (MCrs || MTxEn);
|
if(PassAll)
|
if ((MCrs == 1'b1) && (MTxEn == 1'b0)) // defer TX due to Carrier Sense
|
begin
|
|
if(enable_irq_in_rxbd)
|
|
begin
|
begin
|
if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
|
@(posedge mrx_clk);
|
|
#2;
|
|
if (MTxEn == 1'b0)
|
begin
|
begin
|
$display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
wait (MColl);
|
$display("RxBD = 0x%0x", data);
|
`TIME; $display("*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision");
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
test_fail("Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision");
|
fail = fail + 1;
|
fail = fail + 1;
|
|
coll = 1;
|
|
end
|
end
|
end
|
end
|
end
|
else
|
|
begin
|
begin
|
if(data !== 32'h402100) // Rx BD must not be marked as EMPTY (control frame is received)
|
wait (MCrs || MTxEn);
|
|
#1;
|
|
if ((MCrs == 1'b1) && (MTxEn == 1'b0)) // defer TX due to Carrier Sense
|
begin
|
begin
|
$display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
@(posedge mrx_clk);
|
$display("RxBD = 0x%0x", data);
|
#2;
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
if (MTxEn == 1'b0)
|
fail = fail + 1;
|
$display(" ->TX Defer occured");
|
end
|
|
end
|
|
end
|
|
else
|
else
|
begin
|
begin
|
if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
|
$display(" ->Collision occured due to registered inputs");
|
begin
|
coll = 1;
|
$display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
$display("RxBD = 0x%0x", data);
|
|
test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
fail = fail + 1;
|
|
end
|
end
|
end
|
end
|
// Checking if interrupt was generated
|
else
|
if (wb_int)
|
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
|
wait (MColl);
|
test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
|
$display(" ->Collision occured - last checking");
|
fail = fail + 1;
|
num_of_frames = 35; // this was last transmission
|
|
coll = 1;
|
|
tmp_len = eth_phy.tx_len; // without preamble and SFD (bytes)
|
end
|
end
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
repeat(10) @(posedge mrx_clk);
|
if(RxFlow)
|
repeat(8) @(posedge wb_clk);
|
begin
|
#1 check_tx_bd(tx_bd_num, data);
|
if(data !== (`ETH_INT_RXC))
|
if (data[15] === 0) // transmit should not be aborted aborted
|
begin
|
begin
|
test_fail("RXC is not set or multiple IRQs active!");
|
`TIME; $display("*E Transmit should not be aborted due to TX Defer or Collision");
|
|
test_fail("Transmit should not be aborted due to TX Defer or Collision");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
disable retransmit0;
|
end
|
end
|
// Clear RXC interrupt
|
// check if RX frame is accepted
|
wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
|
wait (MRxDV === 1'b0); // end receive
|
end
|
repeat(10) @(posedge mrx_clk);
|
else if(enable_irq_in_rxbd)
|
repeat(8) @(posedge wb_clk);
|
begin
|
disable collision0;
|
if(data !== (`ETH_INT_RXB))
|
#1 check_rx_bd(rx_bd_num, data);
|
|
if (data[15] === 1)
|
begin
|
begin
|
test_fail("RXB is not set or multiple IRQs active!");
|
`TIME; $display("*E Receive packet should be accepted");
|
|
test_fail("Receive packet should be accepted");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
end
|
else
|
else
|
begin
|
check_rx_frame = 1'b1; // RX frame accepted and must be checked
|
if(data !== 0)
|
repeat(1) @(posedge wb_clk);
|
begin
|
|
test_fail("Some IRQs is active!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
end
|
end
|
if(RxFlow)
|
begin: retransmit0
|
begin
|
// check for retransmission of packet
|
if(MTxEn) // If pause frame was received OK, transmission of the data packet should not start
|
wait (MRxDV === 1'b1); // start receive
|
|
wait (MRxDV === 1'b0); // end receive
|
|
while (MTxEn == 0) // start of retransmission, IPGR2 counting
|
begin
|
begin
|
`TIME; $display("*E Transmission should not be started because pause frame was received.");
|
i = i + 1;
|
test_fail("Transmission should not be started because pause frame was received.");
|
@(posedge mrx_clk);
|
fail = fail + 1;
|
#2;
|
end
|
end
|
while(pause_value)
|
$display(" ->IPGR2 timing checking");
|
|
wait (MTxEn === 1'b0); // end of retransmission
|
|
if (i < (ipgr2 + 6))
|
begin
|
begin
|
pause_value=pause_value-1;
|
`TIME; $display("*E Wrong IPGR2 timing when retransmitting: %0d instead of %0d", i, (ipgr2 + 6));
|
repeat(2*64) @(posedge mtx_clk); // Wait for the time needed for the pause (1 slot).
|
test_fail("Wrong IPGR2 timing when retransmitting");
|
if((!pause_value) && (!MTxEn)) // Transmission should be enabled now.
|
|
begin
|
|
`TIME; $display("*E Transmission should be started because pause passed.");
|
|
test_fail("Transmission should be started because pause passed.");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
else if((pause_value) && (MTxEn)) // Transmission should not be enabled now.
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(8) @(posedge wb_clk);
|
|
#1 check_tx_bd(tx_bd_num, data);
|
|
if (data[15] === 1)
|
begin
|
begin
|
`TIME; $display("*E Transmission should still be paused.");
|
`TIME; $display("*E Re-Transmit should be transmitted");
|
test_fail("Transmission should still be paused.");
|
test_fail("Re-Transmit should be transmitted");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
|
end
|
|
else
|
else
|
begin
|
check_tx_frame = 1;
|
if(!MTxEn) // Pause frame was not received because RxFlow is turned off.
|
repeat(1) @(posedge wb_clk);
|
begin
|
|
`TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
|
|
test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
end
|
wait(wb_int); // Wait antil frame transmission is over and irq generated
|
join
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
repeat(10) @(posedge mrx_clk);
|
if(data !== (`ETH_INT_TXB))
|
repeat(10) @(posedge wb_clk);
|
|
// check RX packet
|
|
check_rx_bd(rx_bd_num, data);
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length))
|
begin
|
begin
|
test_fail("TXB is not set or multiple IRQs active!");
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length));
|
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear TXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
|
// End: Test is irq is set while RXB and RXC interrupts are masked.
|
|
|
|
// Now all interrupts are unmasked. Performing tests again.
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
for (i=0; i<4; i=i+1)
|
|
begin
|
|
pause_value = i+1;
|
|
set_rx_control_packet(0, pause_value); // CRC already appended
|
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
|
case (i)
|
|
0: // PASSALL = 0, RXFLOW = 0
|
|
begin
|
|
PassAll=0; RxFlow=0;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
end
|
1: // PASSALL = 0, RXFLOW = 1
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, (`MEMORY_BASE), (i_length), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
begin
|
begin
|
PassAll=0; RxFlow=1;
|
`TIME; $display("*E Wrong data of the received packet");
|
// enable interrupt generation
|
test_fail("Wrong data of the received packet");
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
fail = fail + 1;
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
end
|
2: // PASSALL = 1, RXFLOW = 0
|
// check RX buffer descriptor of a packet
|
|
if (~coll) // if no collision
|
begin
|
begin
|
PassAll=1; RxFlow=0;
|
if ( (data[15:0] !== 16'h6080) && // wrap bit
|
// enable interrupt generation
|
(data[15:0] !== 16'h4080) ) // without wrap bit
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
default: // 3: PASSALL = 1, RXFLOW = 1
|
|
begin
|
begin
|
PassAll=1; RxFlow=1;
|
`TIME;
|
// enable interrupt generation
|
if (num_of_frames[1:0] == 2'h3)
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
$display("*E RX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h6080);
|
// Set PASSALL = 1 and RXFLOW = 1
|
else
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
$display("*E RX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h4080);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
end
|
end
|
endcase
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
// set wrap bit and empty bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
// transmit
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
end
|
|
else
|
begin
|
begin
|
#1 check_rx_bd(127, data);
|
if ( (data[15:0] !== 16'h6081) && // wrap bit
|
wait (MRxDV === 1'b1); // start transmit
|
(data[15:0] !== 16'h4081) ) // without wrap bit
|
#1 check_rx_bd(127, data);
|
begin
|
if (data[15] !== 1)
|
`TIME;
|
begin
|
if (num_of_frames[1:0] == 2'h3)
|
$display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
$display("*E RX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h6081);
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h4081);
|
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MRxDV === 1'b0); // end transmit
|
end
|
repeat(50) @(posedge mrx_clk); // Wait some time so frame is received and
|
|
repeat (100) @(posedge wb_clk); // status/irq is written.
|
|
|
|
if(RxFlow) // Waiting x slot times before continuing so pause is deactivated.
|
// check TX packet
|
repeat(64 * 2 * pause_value) @(posedge mrx_clk);
|
check_tx_bd(tx_bd_num, data);
|
|
// check length of a PACKET
|
|
if (eth_phy.tx_len != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from MAC: %0d instead of %0d",
|
|
eth_phy.tx_len, (i_length + 4));
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
end
|
end
|
join
|
// check transmitted TX packet data and CRC
|
#1 check_rx_bd(127, data);
|
check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames), (i_length), tmp);
|
// Checking buffer descriptor
|
if (tmp > 0)
|
if(PassAll)
|
|
begin
|
begin
|
if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
|
`TIME; $display("*E Wrong data of the transmitted packet");
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check TX buffer descriptor of a packet
|
|
if (~coll) // if no collision
|
begin
|
begin
|
$display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
if ( (data[15:0] !== 16'h7802) && // wrap bit
|
$display("RxBD = 0x%0x", data);
|
(data[15:0] !== 16'h5802) ) // without wrap bit
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
begin
|
|
`TIME;
|
|
if (num_of_frames[1:0] == 2'h3)
|
|
$display("*E TX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h7802);
|
|
else
|
|
$display("*E TX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h5802);
|
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
|
if ( (data[15:0] !== 16'h7810) && // wrap bit
|
|
(data[15:0] !== 16'h5810) ) // without wrap bit
|
begin
|
begin
|
$display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
`TIME;
|
$display("RxBD = 0x%0x", data);
|
if (num_of_frames[1:0] == 2'h3)
|
test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
$display("*E TX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h7810);
|
|
else
|
|
$display("*E TX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h5810);
|
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// Checking if interrupt was generated
|
|
if(RxFlow || PassAll)
|
// check RX & TX
|
begin
|
// check WB INT signal
|
if (!wb_int)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
// check interrupts
|
else
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (~coll)
|
begin
|
begin
|
if (wb_int)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("WB INT signal should not be set");
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
else
|
if(RxFlow)
|
|
begin
|
begin
|
if(data !== (`ETH_INT_RXC))
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
begin
|
begin
|
test_fail("RXC is not set or multiple IRQs active!");
|
`TIME; $display("*E Interrupt Receive Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Error was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
end
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
end
|
else if(PassAll)
|
if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
|
begin
|
begin
|
if(data !== (`ETH_INT_RXB))
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Transmit Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if (~coll)
|
begin
|
begin
|
test_fail("RXB is not set or multiple IRQs active!");
|
if ((data & (~(`ETH_INT_RXB | `ETH_INT_TXB))) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive & Transmit Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive & Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
end
|
// Clear RXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(data !== 0)
|
if ((data & (~(`ETH_INT_RXE | `ETH_INT_TXB))) !== 0)
|
begin
|
begin
|
test_fail("No interrupt should be set!");
|
`TIME; $display("*E Other interrupts (except Receive Error & Transmit Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Error & Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
|
|
end
|
end
|
end
|
end
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
//// corrupt RX data in RX BD memory
|
|
//wait (wbm_working == 0);
|
|
//wbm_write(`MEMORY_BASE, 32'hDEAD_BEEF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
//wbm_write(`MEMORY_BASE + 4, 32'hBEEF_DEAD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// the number of frame transmitted
|
|
if ((num_of_frames == 3) || (num_of_frames == 7) || (num_of_frames == 11) || (num_of_frames == 15) ||
|
|
(num_of_frames == 19) || (num_of_frames == 23) || (num_of_frames == 27) || (num_of_frames == 31))
|
|
begin
|
|
tx_bd_num = 0; // tx BDs go from 0 to 3
|
|
rx_bd_num = 4; // rx BDs go from 4 to 7
|
|
set_tx_bd(0, 3, i_length[15:0], 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
|
set_tx_bd_wrap(3);
|
|
set_rx_bd(4, 7, 1'b1, `MEMORY_BASE);
|
|
set_rx_bd_wrap(7);
|
|
set_rx_bd_empty(4, 7);
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(10) @(posedge wb_clk);
|
|
end
|
|
else
|
|
begin
|
|
tx_bd_num = tx_bd_num + 1; // tx BDs go from 0 to 3
|
|
rx_bd_num = rx_bd_num + 1; // rx BDs go from 4 to 7
|
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
repeat(50) @(posedge mrx_clk);
|
end
|
end
|
// disable RX
|
// disable RX
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wait (wbm_working == 0);
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
@(posedge wb_clk);
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Receive control frames with PASSALL option turned on and ////
|
//// Test defer and collision with IPGR2 while transmitting ////
|
//// off. Using only one RX buffer decriptor ( 100Mbps ). ////
|
//// and receiving normal frames. Using 4 TX and RX buffer ////
|
|
//// decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) //
|
if (test_num == 1) //
|
begin
|
begin
|
// TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )
|
// TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )
|
test_name = "TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )";
|
//
|
`TIME; $display(" TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )");
|
test_name = "TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )";
|
|
`TIME; $display(" TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )");
|
|
|
// unmask interrupts
|
// reset MAC completely
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
hard_reset;
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set wb slave response
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
max_tmp = 0;
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
min_tmp = 0;
|
|
// set 4 TX buffer descriptors (4 TX and 4 RX BDs will be used) - must be set before TX/RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable TX and RX, set half-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_RXEN | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX_FLOW control
|
// prepare two packets for TX and RX
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wait (wbm_working == 0);
|
// prepare one packet of 100 bytes long
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// st_data = 8'h1A;
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
// set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
min_tmp = tmp[31:16];
|
// append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
|
st_data = 8'h17;
|
st_data = 8'h01;
|
set_rx_packet(0, (min_tmp), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_tx_packet(`MEMORY_BASE + 64, 100, 8'h01); // length without CRC
|
append_rx_crc (0, (min_tmp), 1'b0, 1'b0);
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
|
st_data = 8'h92;
|
set_tx_bd_wrap(0);
|
set_tx_packet(`MEMORY_BASE, (min_tmp), st_data); // length without CRC
|
|
append_tx_crc (`MEMORY_BASE, (min_tmp), 1'b0);
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h0_00; // bit 6 reset - (10/100), bit 8 set - HD
|
speed = 100;
|
speed = 100;
|
|
|
// RXB and RXC interrupts masked
|
// set TX and RX Buffer Descriptors
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
|
tx_bd_num = 0; // tx BDs go from 0 to 3
|
`ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
rx_bd_num = 4; // rx BDs go from 4 to 7
|
// Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
|
ipgr2 = 0;
|
for (i=0; i<3; i=i+1)
|
i_length = min_tmp + 4;
|
begin
|
set_tx_bd(0, 3, i_length[15:0], 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
pause_value = i+2;
|
set_tx_bd_wrap(3);
|
set_rx_control_packet(0, pause_value); // CRC already appended
|
set_rx_bd(4, 7, 1'b1, `MEMORY_BASE);
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
set_rx_bd_wrap(7);
|
case (i)
|
set_rx_bd_empty(4, 7);
|
0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
|
|
begin
|
|
PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
|
|
begin
|
|
PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
|
|
begin
|
|
PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
default:
|
|
begin
|
|
`TIME; $display("*E We should never get here !!!");
|
|
test_fail("We should never get here !!!");
|
|
fail = fail + 1;
|
|
end
|
|
endcase
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
// set wrap bit and empty bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
// transmit
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
end
|
repeat(10) @(posedge wb_clk);
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
num_of_frames = 0;// 0; // 10;
|
#1 check_rx_bd(127, data);
|
while (num_of_frames <= 83)
|
if (data[15] !== 1)
|
|
begin
|
begin
|
`TIME; $display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
st_data = 8'h2 + num_of_frames;
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
set_rx_packet(0, (min_tmp), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
fail = fail + 1;
|
append_rx_crc (0, (min_tmp), 1'b0, 1'b0);
|
end
|
eth_phy.set_tx_mem_addr(num_of_frames);
|
wait (MRxDV === 1'b0); // received pause frame
|
// CHECK END OF RECEIVE WHILE TRANSMITTING
|
repeat(5) @(posedge mrx_clk); // Wait some time so pause is activated.
|
if (num_of_frames == 0)
|
repeat(5) @(posedge mtx_clk); // Wait some time so pause is activated.
|
|
set_tx_bd_ready(0, 0); // Request sending the data. Data should not be sent when pause frame was received
|
|
// and RxFlow enabled.
|
|
// When we exit the while loop, status frame is received
|
|
repeat(`ETH_TX_FIFO_DEPTH) @(eth_ma_wb_ack_i); // Waiting until TX fifo is filled.
|
|
repeat(10) @(posedge mtx_clk); // Wait some time for tx start.
|
|
end
|
|
join
|
|
#1 check_rx_bd(127, data);
|
|
// Checking buffer descriptor
|
|
if(PassAll)
|
|
begin
|
begin
|
if(enable_irq_in_rxbd)
|
ipgr2 = 7'h0;
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_IPGR2, ipgr2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
if (num_of_frames == 1)
|
begin
|
begin
|
if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
|
ipgr2 = 7'h1;
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_IPGR2, ipgr2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
if (num_of_frames == 2)
|
begin
|
begin
|
`TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
ipgr2 = 7'h12;
|
$display("RxBD = 0x%0x", data);
|
wait (wbm_working == 0);
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
wbm_write(`ETH_IPGR2, ipgr2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
fail = fail + 1;
|
end
|
|
frame_ended = 0;
|
|
check_rx_frame = 0;
|
|
check_tx_frame = 0;
|
|
i = 0;
|
|
coll = 0;
|
|
fork
|
|
// send frames
|
|
begin // start with RX frame
|
|
repeat(num_of_frames) @(posedge mrx_clk);
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, i_length, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
end
|
end
|
|
begin // start with TX frame
|
|
repeat(4) @(posedge mrx_clk);
|
|
repeat(2) @(posedge wb_clk);
|
|
#1 set_tx_bd_ready(tx_bd_num, tx_bd_num);
|
end
|
end
|
else
|
// observe TX Enable, Carrier Sense and Collision - TX frame is not repeated after Late Collision
|
|
begin: collision1
|
|
wait (MCrs || MTxEn);
|
|
if ((MCrs == 1'b1) && (MTxEn == 1'b0)) // defer TX due to Carrier Sense
|
begin
|
begin
|
if(data !== 32'h402100) // Rx BD must not be marked as EMPTY (control frame is received)
|
@(posedge mrx_clk);
|
|
#2;
|
|
if (MTxEn == 1'b0)
|
begin
|
begin
|
`TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
wait (MColl);
|
$display("RxBD = 0x%0x", data);
|
`TIME; $display("*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision");
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
test_fail("Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision");
|
fail = fail + 1;
|
fail = fail + 1;
|
|
coll = 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
else
|
|
begin
|
begin
|
if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
|
wait (MCrs || MTxEn);
|
|
#1;
|
|
if ((MCrs == 1'b1) && (MTxEn == 1'b0)) // defer TX due to Carrier Sense
|
begin
|
begin
|
`TIME; $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
@(posedge mrx_clk);
|
$display("RxBD = 0x%0x", data);
|
#2;
|
test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
if (MTxEn == 1'b0)
|
fail = fail + 1;
|
$display(" ->TX Defer occured");
|
|
else
|
|
begin
|
|
$display(" ->Collision occured due to registered inputs");
|
|
coll = 1;
|
end
|
end
|
end
|
end
|
// Checking if interrupt was generated
|
else
|
if (wb_int)
|
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
|
wait (MColl);
|
test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
|
$display(" ->Collision occured - last checking");
|
fail = fail + 1;
|
num_of_frames = 83; // this was last transmission
|
|
coll = 1;
|
|
tmp_len = eth_phy.tx_len; // without preamble and SFD (bytes)
|
end
|
end
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
repeat(10) @(posedge mrx_clk);
|
if(RxFlow)
|
repeat(8) @(posedge wb_clk);
|
begin
|
#1 check_tx_bd(tx_bd_num, data);
|
if(data !== (`ETH_INT_RXC))
|
if (data[15] === 0) // transmit should not be aborted aborted
|
begin
|
begin
|
test_fail("RXC is not set or multiple IRQs active!");
|
`TIME; $display("*E Transmit should not be aborted due to TX Defer or Collision");
|
|
test_fail("Transmit should not be aborted due to TX Defer or Collision");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
disable retransmit1;
|
end
|
end
|
// Clear RXC interrupt
|
// check if RX frame is accepted
|
wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
|
wait (MRxDV === 1'b0); // end receive
|
end
|
repeat(10) @(posedge mrx_clk);
|
else if(enable_irq_in_rxbd)
|
repeat(8) @(posedge wb_clk);
|
begin
|
disable collision1;
|
if(data !== (`ETH_INT_RXB))
|
#1 check_rx_bd(rx_bd_num, data);
|
|
if (data[15] === 1)
|
begin
|
begin
|
test_fail("RXB is not set or multiple IRQs active!");
|
`TIME; $display("*E Receive packet should be accepted");
|
|
test_fail("Receive packet should be accepted");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
end
|
else
|
else
|
|
check_rx_frame = 1'b1; // RX frame accepted and must be checked
|
|
repeat(1) @(posedge wb_clk);
|
|
end
|
|
begin: retransmit1
|
|
// check for retransmission of packet
|
|
wait (MRxDV === 1'b1); // start receive
|
|
wait (MRxDV === 1'b0); // end receive
|
|
while (MTxEn == 0) // start of retransmission, IPGR2 counting
|
begin
|
begin
|
if(data !== 0)
|
i = i + 1;
|
|
@(posedge mrx_clk);
|
|
#2;
|
|
end
|
|
$display(" ->IPGR2 timing checking");
|
|
wait (MTxEn === 1'b0); // end of retransmission
|
|
if (i < (ipgr2 + 6))
|
begin
|
begin
|
test_fail("Some IRQs is active!");
|
`TIME; $display("*E Wrong IPGR2 timing when retransmitting: %0d instead of %0d", i, (ipgr2 + 6));
|
|
test_fail("Wrong IPGR2 timing when retransmitting");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
|
|
end
|
|
end
|
end
|
if(RxFlow)
|
repeat(10) @(posedge mrx_clk);
|
begin
|
repeat(8) @(posedge wb_clk);
|
if(MTxEn) // If pause frame was received OK, transmission of the data packet should not start
|
#1 check_tx_bd(tx_bd_num, data);
|
|
if (data[15] === 1)
|
begin
|
begin
|
`TIME; $display("*E Transmission should not be started because pause frame was received.");
|
`TIME; $display("*E Re-Transmit should be transmitted");
|
test_fail("Transmission should not be started because pause frame was received.");
|
test_fail("Re-Transmit should be transmitted");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
while(pause_value)
|
else
|
begin
|
check_tx_frame = 1;
|
pause_value=pause_value-1;
|
repeat(1) @(posedge wb_clk);
|
repeat(2*64) @(posedge mtx_clk); // Wait for the time needed for the pause (1 slot).
|
end
|
if((!pause_value) && (!MTxEn)) // Transmission should be enabled now.
|
join
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(10) @(posedge wb_clk);
|
|
// check RX packet
|
|
check_rx_bd(rx_bd_num, data);
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length))
|
begin
|
begin
|
`TIME; $display("*E Transmission should be started because pause passed.");
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
test_fail("Transmission should be started because pause passed.");
|
data[31:16], (i_length));
|
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
else if((pause_value) && (MTxEn)) // Transmission should not be enabled now.
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, (`MEMORY_BASE), (i_length), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
begin
|
begin
|
`TIME; $display("*E Transmission should still be paused.");
|
`TIME; $display("*E Wrong data of the received packet");
|
test_fail("Transmission should still be paused.");
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
// check RX buffer descriptor of a packet
|
end
|
if (~coll) // if no collision
|
else
|
|
begin
|
begin
|
if(!MTxEn) // Pause frame was not received because RxFlow is turned off.
|
if ( (data[15:0] !== 16'h6080) && // wrap bit
|
|
(data[15:0] !== 16'h4080) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
|
`TIME;
|
test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
|
if (num_of_frames[1:0] == 2'h3)
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h6080);
|
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h4080);
|
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
wait(wb_int); // Wait antil frame transmission is over and irq generated
|
else
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(data !== (`ETH_INT_TXB))
|
|
begin
|
begin
|
test_fail("TXB is not set or multiple IRQs active!");
|
if ( (data[15:0] !== 16'h6081) && // wrap bit
|
|
(data[15:0] !== 16'h4081) ) // without wrap bit
|
|
begin
|
|
`TIME;
|
|
if (num_of_frames[1:0] == 2'h3)
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h6081);
|
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h4081);
|
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E TXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
end
|
// Clear TXB interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
end
|
// End: Test is irq is set while RXB and RXC interrupts are masked.
|
|
|
|
// Now all interrupts are unmasked. Performing tests again.
|
// check TX packet
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
check_tx_bd(tx_bd_num, data);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check length of a PACKET
|
for (i=0; i<4; i=i+1)
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
|
pause_value = i+1;
|
|
set_rx_control_packet(0, pause_value); // CRC already appended
|
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
|
case (i)
|
|
0: // PASSALL = 0, RXFLOW = 0
|
|
begin
|
begin
|
PassAll=0; RxFlow=0;
|
`TIME; $display("*E Wrong length of the packet out from MAC %0d instead of %0d",
|
// enable interrupt generation
|
eth_phy.tx_len, (i_length + 4));
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
test_fail("Wrong length of the packet out from MAC");
|
// Set PASSALL = 0 and RXFLOW = 0
|
fail = fail + 1;
|
wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
end
|
1: // PASSALL = 0, RXFLOW = 1
|
// check transmitted TX packet data and CRC
|
|
check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames), (i_length), tmp);
|
|
if (tmp > 0)
|
begin
|
begin
|
PassAll=0; RxFlow=1;
|
`TIME; $display("*E Wrong data of the transmitted packet");
|
// enable interrupt generation
|
test_fail("Wrong data of the transmitted packet");
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
fail = fail + 1;
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
end
|
2: // PASSALL = 1, RXFLOW = 0
|
// check TX buffer descriptor of a packet
|
|
if (~coll) // if no collision
|
begin
|
begin
|
PassAll=1; RxFlow=0;
|
if ( (data[15:0] !== 16'h7802) && // wrap bit
|
// enable interrupt generation
|
(data[15:0] !== 16'h5802) ) // without wrap bit
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// Set PASSALL = 0 and RXFLOW = 0
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
default: // 3: PASSALL = 1, RXFLOW = 1
|
|
begin
|
begin
|
PassAll=1; RxFlow=1;
|
`TIME;
|
// enable interrupt generation
|
if (num_of_frames[1:0] == 2'h3)
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
$display("*E TX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h7802);
|
// Set PASSALL = 1 and RXFLOW = 1
|
else
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
$display("*E TX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h5802);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
end
|
end
|
endcase
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
// set wrap bit and empty bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
// transmit
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
end
|
|
else
|
begin
|
begin
|
#1 check_rx_bd(127, data);
|
if ( (data[15:0] !== 16'h7810) && // wrap bit
|
wait (MRxDV === 1'b1); // start transmit
|
(data[15:0] !== 16'h5810) ) // without wrap bit
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
begin
|
$display("*E Wrong buffer descriptor's ready bit read out from MAC");
|
`TIME;
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
if (num_of_frames[1:0] == 2'h3)
|
|
$display("*E TX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h7810);
|
|
else
|
|
$display("*E TX buffer descriptor status is not correct: %0h instead of %0h", data[15:0], 'h5810);
|
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MRxDV === 1'b0); // end transmit
|
end
|
repeat(50) @(posedge mrx_clk); // Wait some time so frame is received and
|
|
repeat (100) @(posedge wb_clk); // status/irq is written.
|
|
|
|
if(RxFlow) // Waiting x slot times before continuing so pause is deactivated.
|
// check RX & TX
|
repeat(64 * 2 * pause_value) @(posedge mrx_clk);
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
end
|
end
|
join
|
// check interrupts
|
#1 check_rx_bd(127, data);
|
wait (wbm_working == 0);
|
// Checking buffer descriptor
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if(PassAll)
|
if (~coll)
|
begin
|
begin
|
if(data !== 32'h406100) // Rx BD must not be marked as EMPTY (control frame is received)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
$display("RxBD = 0x%0x", data);
|
test_fail("Interrupt Receive Buffer was not set");
|
test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(data !== 32'he000) // Rx BD must be marked as EMPTY (no packet received)
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
begin
|
begin
|
`TIME; $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
`TIME; $display("*E Interrupt Receive Error was not set, interrupt reg: %0h", data);
|
$display("RxBD = 0x%0x", data);
|
test_fail("Interrupt Receive Error was not set");
|
test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// Checking if interrupt was generated
|
if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
|
|
|
if(RxFlow | PassAll)
|
|
begin
|
|
if (!wb_int)
|
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
test_fail("WB INT signal should be set");
|
test_fail("Interrupt Transmit Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
if (~coll)
|
else
|
|
begin
|
begin
|
if (wb_int)
|
if ((data & (~(`ETH_INT_RXB | `ETH_INT_TXB))) !== 0)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E Other interrupts (except Receive & Transmit Buffer) were set, interrupt reg: %0h", data);
|
test_fail("WB INT signal should not be set");
|
test_fail("Other interrupts (except Receive & Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
else
|
if(RxFlow)
|
|
begin
|
begin
|
if(data !== (`ETH_INT_RXC))
|
if ((data & (~(`ETH_INT_RXE | `ETH_INT_TXB))) !== 0)
|
begin
|
begin
|
test_fail("RXC is not set or multiple IRQs active!");
|
`TIME; $display("*E Other interrupts (except Receive Error & Transmit Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Error & Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
end
|
// Clear RXC interrupt
|
|
wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
|
|
end
|
end
|
else if(PassAll)
|
// clear interrupts
|
begin
|
wait (wbm_working == 0);
|
if(data !== (`ETH_INT_RXB))
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("RXB is not set or multiple IRQs active!");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
|
|
end
|
end
|
// Clear RXB interrupt
|
//// corrupt RX data in RX BD memory
|
wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
|
//wait (wbm_working == 0);
|
|
//wbm_write(`MEMORY_BASE, 32'hDEAD_BEEF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
//wbm_write(`MEMORY_BASE + 4, 32'hBEEF_DEAD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// the number of frame transmitted
|
|
if ((num_of_frames == 3) || (num_of_frames == 7) || (num_of_frames == 11) || (num_of_frames == 15) ||
|
|
(num_of_frames == 19) || (num_of_frames == 23) || (num_of_frames == 27) || (num_of_frames == 31) ||
|
|
(num_of_frames == 35) || (num_of_frames == 39) || (num_of_frames == 43) || (num_of_frames == 47) ||
|
|
(num_of_frames == 51) || (num_of_frames == 55) || (num_of_frames == 59) || (num_of_frames == 63) ||
|
|
(num_of_frames == 67) || (num_of_frames == 71) || (num_of_frames == 75) || (num_of_frames == 79))
|
|
begin
|
|
tx_bd_num = 0; // tx BDs go from 0 to 3
|
|
rx_bd_num = 4; // rx BDs go from 4 to 7
|
|
set_tx_bd(0, 3, i_length[15:0], 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
|
set_tx_bd_wrap(3);
|
|
set_rx_bd(4, 7, 1'b1, `MEMORY_BASE);
|
|
set_rx_bd_wrap(7);
|
|
set_rx_bd_empty(4, 7);
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(10) @(posedge wb_clk);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(data !== 0)
|
tx_bd_num = tx_bd_num + 1; // tx BDs go from 0 to 3
|
begin
|
rx_bd_num = rx_bd_num + 1; // rx BDs go from 4 to 7
|
test_fail("No interrupt should be set!");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
|
|
end
|
|
end
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
repeat(50) @(posedge mrx_clk);
|
end
|
end
|
// disable RX
|
// disable RX
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wait (wbm_working == 0);
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
@(posedge wb_clk);
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Receive control frames with PASSALL option turned on and ////
|
//// Test collision and late collision while transmitting and ////
|
//// off. Using only one RX buffer decriptor ( 10Mbps ). ////
|
//// receiving normal frames. Using 4 TX and RX buffer ////
|
|
//// decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 4) //
|
if (test_num == 2) //
|
begin
|
begin
|
// TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )
|
// TEST 2: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )
|
test_name = "TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )";
|
//
|
`TIME; $display(" TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )");
|
test_name = "TEST 2: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )";
|
|
`TIME; $display(" TEST 2: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )");
|
|
|
// unmask interrupts
|
// reset MAC completely
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
hard_reset;
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set wb slave response
|
// set 1 TX and 1 RX buffer descriptor (8'h01) - must be set before RX enable
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wbm_write(`ETH_TX_BD_NUM, 32'h01, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
max_tmp = 0;
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
min_tmp = 0;
|
|
// set 4 TX buffer descriptors (4 TX and 4 RX BDs will be used) - must be set before TX/RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable TX and RX, set half-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_RXEN | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable flow control
|
// prepare two packets of MAXFL length for TX and RX
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
|
min_tmp = tmp[31:16];
|
|
st_data = 8'h17;
|
|
set_rx_packet(0, (min_tmp), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, (min_tmp), 1'b0, 1'b0);
|
|
st_data = 8'h92;
|
|
set_tx_packet(`MEMORY_BASE, (min_tmp), st_data); // length without CRC
|
|
append_tx_crc (`MEMORY_BASE, (min_tmp), 1'b0);
|
|
|
wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW | `ETH_CTRLMODER_TXFLOW,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// prepare one RX and one TX packet of 100 bytes long
|
|
rx_len = 100; // length of frame without CRC
|
|
st_data = 8'h1A;
|
|
set_rx_packet(200, rx_len, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
|
append_rx_crc (200, rx_len, 1'b0, 1'b0); // CRC for data packet
|
|
tx_len = 64; // length of frame without CRC
|
|
st_data = 8'h01;
|
|
set_tx_packet(`MEMORY_BASE + 64, tx_len, st_data); // length without CRC
|
|
// set TX and RX Buffer Descriptors
|
|
tx_bd_num = 0; // tx BDs go from 0 to 0
|
|
rx_bd_num = 1; // rx BDs go from 1 to 1
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// unmask interrupts
|
// set EQUAL mrx_clk to mtx_clk!
|
wait (wbm_working == 0);
|
// eth_phy.set_mrx_equal_mtx = 1'b1;
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - HD
|
speed = 10;
|
speed = 10;
|
|
|
// TXB and RXB interrupts masked
|
// set TX and RX Buffer Descriptors
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY | `ETH_INT_TXC | `ETH_INT_RXC,
|
tx_bd_num = 0; // tx BDs go from 0 to 3
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
rx_bd_num = 4; // rx BDs go from 4 to 7
|
|
set_tx_bd(0, 3, i_length[15:0], 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
|
set_tx_bd_wrap(3);
|
|
set_rx_bd(4, 7, 1'b1, `MEMORY_BASE);
|
|
set_rx_bd_wrap(7);
|
|
set_rx_bd_empty(4, 7);
|
|
|
|
// frame_ended = 0;
|
tmp_len = 0;
|
tmp_len = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;// 0; // 10;
|
num_of_rx_frames = 0;
|
num_of_iter = 0;
|
// num_of_iter = 0;
|
// num_of_bd = 0;
|
// TX frame loop & RX frame loop work independently
|
// i_length = 0;// (0 - 4); // 6; // 4 less due to CRC
|
|
while (num_of_frames < 80)
|
|
begin
|
|
// change COLLVALID bits in COLLCONF register
|
|
if ((num_of_frames == 0) && (num_of_iter == 0))
|
|
begin
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
tmp[5:0] = 6'h00; // 6'b00_0000 -> 0 + 1 = 1 byte from preamble
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
$display(" Collision window is set to 1 byte after preamble and SFD");
|
|
end
|
|
else if ((num_of_frames == 0) && (num_of_iter == 1))
|
|
begin
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
tmp[5:0] = 6'h15; // 6'b01_0101 -> 21 + 1 = 22 bytes from preamble
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
$display(" Collision window is set to 22 bytes after preamble and SFD");
|
|
end
|
|
else if ((num_of_frames == 0) && (num_of_iter == 2))
|
|
begin
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
tmp[5:0] = 6'h2A; // 6'b10_1010 -> 42 + 1 = 43 bytes from preamble
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
$display(" Collision window is set to 43 bytes after preamble and SFD");
|
|
end
|
|
else if ((num_of_frames == 0) && (num_of_iter == 3))
|
|
begin
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
tmp[5:0] = 6'h3F; // 6'b11_1111 -> 63 + 1 = 64 bytes from preamble
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
$display(" Collision window is set to 64 bytes after preamble and SFD");
|
|
end
|
|
|
|
|
|
//wire MRxDV; // This goes to PHY
|
|
//wire MRxErr; // This goes to PHY
|
|
//wire MColl; // This goes to PHY
|
|
//wire MCrs; // This goes to PHY
|
|
//wire MTxEn;
|
|
//wire MTxErr;
|
|
// CHECK END OF RECEIVE WHILE TRANSMITTING
|
|
frame_ended = 0;
|
|
check_rx_frame = 0;
|
fork
|
fork
|
// TX frame loop
|
// send frames
|
while (num_of_frames < 400)
|
begin // start with RX frame
|
|
repeat(num_of_frames) @(posedge mrx_clk);
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (min_tmp + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin // start with TX frame
|
|
repeat(2) @(posedge mrx_clk);
|
|
repeat(2) @(posedge wb_clk);
|
|
#1 set_tx_bd_ready(tx_bd_num, tx_bd_num);
|
|
end
|
|
// observe TX Enable, Carrier Sense and Collision - TX frame is not repeated after Late Collision
|
begin
|
begin
|
eth_phy.set_tx_mem_addr(64 + num_of_frames);
|
wait (MCrs || MTxEn);
|
// set tx bd
|
#1;
|
// wait for WB master if it is working
|
if ((MCrs == 1'b1) && (MTxEn == 1'b0)) // defer TX due to Carrier Sense
|
@(posedge wb_clk);
|
wait_for_tx_frame = 1'b1; // wait for retransmission of TX frame
|
while (wbm_working)
|
else
|
begin
|
begin
|
@(posedge wb_clk);
|
|
end
|
|
set_tx_bd(0, 0, tx_len, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
|
|
set_tx_bd_wrap(0);
|
|
set_tx_bd_ready(0, 0);
|
|
check_tx_bd(0, data);
|
|
// check frame
|
|
i = 0;
|
i = 0;
|
while((i < 100) && (MTxEn === 1'b0)) // wait for start of TX frame!
|
while (MColl == 1'b0) // wait for Collision to occure
|
begin
|
begin
|
@(posedge mtx_clk);
|
repeat(2) @(posedge mtx_clk); // counting bytes
|
i = i + 1;
|
#1 i = i + 1'b1;
|
end
|
end
|
if (MTxEn != 1'b1)
|
i = i - 8; // subtract preamble and SFD (bytes) - Late Collision is measured from SFD!
|
|
tmp_len = eth_phy.tx_len; // without preamble and SFD (bytes)
|
|
//wait (MTxEn == 1'b0); // wait for TX frame to end
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(8) @(posedge wb_clk);
|
|
#1 check_tx_bd(tx_bd_num, data);
|
|
if (data[15] === 0) // if transmit is aborted, then it was Late Collision
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: MAC TX didn't start transmitting the packet", num_of_frames);
|
wait_for_tx_frame = 1'b0; // don't wait for retransmission of TX frame
|
test_fail("MAC TX didn't start transmitting the packet");
|
$display(" ->Late Collision occured on %0d. byte after frame and SFD", i);
|
fail = fail + 1;
|
end
|
#10000 $stop;
|
else
|
|
wait_for_tx_frame = 1'b1; // wait for retransmission of TX frame
|
|
end
|
|
end
|
|
// check if RX frame is accepted
|
|
begin
|
|
wait (MRxDV === 1'b1); // start receive
|
|
wait (MRxDV === 1'b0); // end receive
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(8) @(posedge wb_clk);
|
|
#1 check_rx_bd(rx_bd_num, data);
|
|
if (data[15] === 0)
|
|
begin
|
|
check_rx_frame = 1'b1; // RX frame accepted and must be checked
|
|
if ((i + 8) == 0) // add preamble and SFD length (bytes)
|
|
$display(" ->RX frame, which started before or at beginning of TX frame, was accepted");
|
|
else
|
|
$display(" ->RX frame, which started %0d byte(s) after beginning of TX frame, was accepted", (i + 8));
|
|
end
|
|
else
|
|
check_rx_frame = 1'b0; // RX frame rejected
|
|
repeat(1) @(posedge wb_clk);
|
end
|
end
|
|
join
|
|
|
|
|
repeat (30) @(posedge mtx_clk); // waiting some time so PHY clears the tx_len
|
|
|
|
wait ((MTxEn === 1'b0) || (eth_phy.tx_len > (tx_len + 4))) // wait for end of TX frame
|
// check length of a PACKET
|
if (MTxEn != 1'b0)
|
if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
|
|
((data[31:16] != 0) && (num_of_frames < 3)) )
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: MAC TX didn't stop transmitting the packet", num_of_frames);
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
test_fail("MAC TX didn't stop transmitting the packet");
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
#10000 $stop;
|
|
end
|
|
tmp_len = eth_phy.tx_len;
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
end
|
end
|
check_tx_bd(0, data);
|
// check received RX packet data and CRC
|
while (data[15] === 1)
|
//if ((num_of_frames == 5))
|
begin
|
//begin // CRC has 4 bytes for itself
|
// wait for WB master if it is working
|
// if (i_length[0] == 1'b1)
|
@(posedge wb_clk);
|
// begin
|
while (wbm_working)
|
// check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
|
// end
|
|
// else
|
|
// begin
|
|
// check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
|
|
// end
|
|
// if (tmp > 0)
|
|
// begin
|
|
// `TIME; $display("*E Wrong data of the received packet");
|
|
// test_fail("Wrong data of the received packet");
|
|
// fail = fail + 1;
|
|
// end
|
|
//end
|
|
//else
|
|
//if ((num_of_frames == 10))
|
|
//begin // CRC has 4 bytes for itself
|
|
// if (i_length[0] == 1'b1)
|
|
// begin
|
|
// check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
|
// end
|
|
// else
|
|
// begin
|
|
// check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
|
|
// end
|
|
// if (tmp > 0)
|
|
// begin
|
|
// `TIME; $display("*E Wrong data of the received packet");
|
|
// test_fail("Wrong data of the received packet");
|
|
// fail = fail + 1;
|
|
// end
|
|
//end
|
|
//else
|
|
if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
|
|
begin // CRC has 4 bytes for itself
|
|
if (i_length[0] == 1'b0)
|
begin
|
begin
|
@(posedge wb_clk);
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
end
|
|
check_tx_bd(0, data);
|
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
else
|
// check length of a PACKET
|
|
if (tmp_len != (tx_len + 4))
|
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: Wrong length of the packet out from MAC (%0d instead of %0d)", num_of_frames,
|
check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
|
tmp_len, (tx_len + 4));
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
end
|
// check transmitted TX packet data
|
|
check_tx_packet((`MEMORY_BASE + 64), (64 + num_of_frames), (tx_len), tmp);
|
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: Wrong data of the transmitted packet", num_of_frames);
|
`TIME; $display("*E Wrong data of the received packet");
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
end
|
check_tx_crc((64 + num_of_frames), (tx_len), 1'b0, tmp); // length without CRC
|
|
if (tmp > 0)
|
// check WB INT signal
|
|
if (num_of_frames >= 3) // Frames smaller than 3 are not received.
|
|
begin // Frames greater then 5 always cause an interrupt (Frame received)
|
|
if (wb_int !== 1'b1) // Frames with length 3 or 4 always cause an interrupt (CRC error)
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: Wrong CRC of the transmitted packet", num_of_frames);
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check WB INT signal
|
end
|
|
else
|
|
begin
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check TX buffer descriptor of a packet
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
end
|
end
|
check_tx_bd(0, data);
|
|
if (data[15:0] !== 16'h7800)
|
// check RX buffer descriptor of a packet
|
|
if (num_of_frames >= min_tmp)
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: TX buffer descriptor status is not correct: %0h", num_of_frames, data[15:0]);
|
if ( (data[15:0] !== 16'h6000) && // wrap bit
|
test_fail("TX buffer descriptor status is not correct");
|
(data[15:0] !== 16'h4000) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check interrupts
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
end
|
end
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
else if (num_of_frames > 4)
|
if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
|
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: Interrupt Transmit Buffer was not set, interrupt reg: %0h", num_of_frames, data);
|
if ( (data[15:0] !== 16'h6004) && // wrap bit
|
test_fail("Interrupt Transmit Buffer was not set");
|
(data[15:0] !== 16'h4004) ) // without wrap bit
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~(`ETH_INT_TXB | `ETH_INT_RXB))) !== 0) // RXB might occur at the same time - not error
|
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: Other interrupts (except Tx and Rx Buffer) were set, interrupt reg: %0h",
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
num_of_frames, data);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// clear interrupts (except RXB)
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
while (wbm_working)
|
|
begin
|
|
@(posedge wb_clk);
|
|
end
|
end
|
wbm_write(`ETH_INT, (data & (~`ETH_INT_RXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
else if (num_of_frames > 2)
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
begin
|
`TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
|
if ( (data[15:0] !== 16'h6006) && // wrap bit
|
test_fail("WB INT signal should not be set");
|
(data[15:0] !== 16'h4006) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// Displays
|
|
if (num_of_frames[2:0] == 3'b111)
|
|
begin
|
|
`TIME; $display(" ->8 frames transmitted");
|
|
end
|
end
|
// set length (loop variable)
|
else
|
num_of_frames = num_of_frames + 1;
|
|
end // TX frame loop
|
|
// RX frame loop
|
|
while (num_of_rx_frames < 400)
|
|
begin
|
begin
|
// set rx bd
|
if (data[15] !== 1'b1)
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
begin
|
@(posedge wb_clk);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
#1;
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
end
|
end
|
set_rx_bd(1, 1, 1'b1, (`MEMORY_BASE + 200 + num_of_rx_frames));
|
|
set_rx_bd_wrap(1);
|
|
set_rx_bd_empty(1, 1);
|
|
// check frame
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 200, (rx_len + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (num_of_frames >= 5)
|
begin
|
begin
|
wait (MRxDV === 1'b1); // start receive
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
begin
|
@(posedge wb_clk);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
#1;
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(1, data);
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
if (data[15] !== 1)
|
|
begin
|
begin
|
`TIME; $display("*E Rx Frame %0d: Wrong buffer descriptor's ready bit read out from MAC", num_of_rx_frames);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MRxDV === 1'b0); // end receive
|
end
|
|
else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
|
while (data[15] === 1)
|
|
begin
|
begin
|
// wait for WB master if it is working
|
if (data) // Checking if any interrupt is pending)
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
begin
|
@(posedge wb_clk);
|
`TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
|
#1;
|
test_fail("Interrupts were set");
|
end
|
fail = fail + 1;
|
check_rx_bd(1, data);
|
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
|
end
|
end
|
join
|
else
|
// check length of a PACKET
|
|
|
|
// Additional read because simulator was not working OK.
|
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
begin
|
@(posedge wb_clk);
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
#1;
|
|
end
|
|
check_rx_bd(1, data);
|
|
|
|
if (data[31:16] != (rx_len + 4))
|
|
begin
|
begin
|
`TIME; $display("*E Rx Frame %0d: Wrong length of the packet written to MAC's register (%0d instead of %0d)",
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
num_of_rx_frames, data[31:16], (rx_len + 4));
|
test_fail("Interrupt Receive Buffer Error was not set");
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check received RX packet data and CRC
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
check_rx_packet(200, (`MEMORY_BASE + 200 + num_of_rx_frames), (rx_len + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
begin
|
`TIME; $display("*E Rx Frame %0d: Wrong data of the received packet", num_of_rx_frames);
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
test_fail("Wrong data of the received packet");
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
`TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
|
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check RX buffer descriptor of a packet
|
// INTERMEDIATE DISPLAYS
|
// wait for WB master if it is working
|
if (num_of_frames == 3)
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
begin
|
@(posedge wb_clk);
|
$display(" using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
|
#1;
|
$display(" ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
|
|
0, 3);
|
end
|
end
|
check_rx_bd(1, data);
|
else if (num_of_frames == 9)
|
if (data[15:0] !== 16'h6080)
|
|
begin
|
begin
|
`TIME; $display("*E Rx Frame %0d: RX buffer descriptor status is not correct: %0h", num_of_rx_frames, data[15:0]);
|
$display(" using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
|
test_fail("RX buffer descriptor status is not correct");
|
$display(" ->packet with length 4 is not received (length increasing by 1 byte)");
|
fail = fail + 1;
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
5, 9);
|
end
|
end
|
// check interrupts
|
else if (num_of_frames == 17)
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
begin
|
@(posedge wb_clk);
|
$display(" using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
|
#1;
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
10, 17);
|
end
|
end
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
else if (num_of_frames == 27)
|
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
begin
|
`TIME; $display("*E Rx Frame %0d: Interrupt Receive Buffer was not set, interrupt reg: %0h",
|
$display(" using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
|
num_of_rx_frames, data);
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
test_fail("Interrupt Receive Buffer was not set");
|
18, 27);
|
fail = fail + 1;
|
|
end
|
end
|
if ((data & (~(`ETH_INT_RXB | `ETH_INT_TXB))) !== 0) // TXB might occur at the same time - not error
|
else if (num_of_frames == 40)
|
begin
|
begin
|
`TIME; $display("*E Rx Frame %0d: Other interrupts (except Rx and Tx Buffer) were set, interrupt reg: %0h",
|
$display(" using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
|
num_of_rx_frames, data);
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
28, 40);
|
fail = fail + 1;
|
|
end
|
end
|
// clear interrupts (except TXB)
|
else if (num_of_frames == 54)
|
// wait for WB master if it is working
|
|
@(posedge wb_clk);
|
|
#1;
|
|
while (wbm_working)
|
|
begin
|
begin
|
@(posedge wb_clk);
|
$display(" using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
|
#1;
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
41, 54);
|
end
|
end
|
wbm_write(`ETH_INT, (data & (~`ETH_INT_TXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
else if (num_of_frames == 69)
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
begin
|
`TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
test_fail("WB INT signal should not be set");
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
fail = fail + 1;
|
55, 69);
|
end
|
end
|
// Displays
|
else if (num_of_frames == 69)
|
if (num_of_rx_frames[2:0] == 3'b111)
|
begin
|
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
55, 69);
|
|
end
|
|
else if (num_of_frames == 77)
|
begin
|
begin
|
`TIME; $display(" ->8 frames received");
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
70, 77);
|
end
|
end
|
// set length (loop variable)
|
// set length (loop variable)
|
num_of_rx_frames = num_of_rx_frames + 1;
|
i_length = i_length + 1;
|
end // RX frame loop
|
// the number of frame transmitted
|
join
|
num_of_frames = num_of_frames + 1;
|
// disable TX & RX
|
if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_PAD | `ETH_MODER_CRCEN |
|
(num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
|
`ETH_MODER_IFG | `ETH_MODER_PRO | `ETH_MODER_BRO,
|
(num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
|
|
(num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
|
|
num_of_bd = 120;
|
|
else
|
|
num_of_bd = num_of_bd + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set DIFFERENT mrx_clk to mtx_clk!
|
@(posedge wb_clk);
|
// eth_phy.set_mrx_equal_mtx = 1'b0;
|
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
|
|
end
|
|
endtask // test_mac_full_duplex_flow_control
|
|
|
|
|
|
task test_mac_half_duplex_flow;
|
|
input [31:0] start_task;
|
|
input [31:0] end_task;
|
|
integer bit_start_1;
|
|
integer bit_end_1;
|
|
integer bit_start_2;
|
|
integer bit_end_2;
|
|
integer num_of_reg;
|
|
integer num_of_frames;
|
|
integer num_of_bd;
|
|
integer num_of_iter;
|
|
integer i_addr;
|
|
integer i_data;
|
|
integer i_length;
|
|
integer tmp_len;
|
|
integer tmp_bd;
|
|
integer tmp_bd_num;
|
|
integer tmp_data;
|
|
integer tmp_ipgt;
|
|
integer test_num;
|
|
reg [31:0] tx_bd_num;
|
|
reg [31:0] rx_bd_num;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
|
|
integer i;
|
|
integer i1;
|
|
integer i2;
|
|
integer i3;
|
|
integer fail;
|
|
integer speed;
|
|
integer mac_hi_addr;
|
|
integer mac_lo_addr;
|
|
reg frame_started;
|
|
reg frame_ended;
|
|
reg check_rx_frame;
|
|
reg wait_for_tx_frame;
|
|
reg [31:0] addr;
|
|
reg [31:0] data;
|
|
reg [31:0] tmp;
|
|
reg [ 7:0] st_data;
|
|
reg [15:0] max_tmp;
|
|
reg [15:0] min_tmp;
|
|
begin
|
|
// MAC HALF DUPLEX FLOW TEST
|
|
test_heading("MAC HALF DUPLEX FLOW TEST");
|
|
$display(" ");
|
|
$display("MAC HALF DUPLEX FLOW TEST");
|
|
fail = 0;
|
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// reset MAC and MII LOGIC with soft reset
|
|
//reset_mac;
|
|
//reset_mii;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
/*
|
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
|
-------------------------------------------------------------------------------------
|
|
set_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
|
|
set_tx_bd_wrap
|
|
(tx_bd_num_end[6:0]);
|
|
set_tx_bd_ready
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
check_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_status[31:0]);
|
|
clear_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and control RX buffer descriptors:
|
|
------------------------------------------------
|
|
set_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
|
|
set_rx_bd_wrap
|
|
(rx_bd_num_end[6:0]);
|
|
set_rx_bd_empty
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
check_rx_bd
|
|
(rx_bd_num_end[6:0], rx_bd_status);
|
|
clear_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and check TX packets:
|
|
-----------------------------------
|
|
set_tx_packet
|
|
(txpnt[31:0], len[15:0], eth_start_data[7:0]);
|
|
check_tx_packet
|
|
(txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
|
|
|
|
TASKS for set and check RX packets:
|
|
-----------------------------------
|
|
set_rx_packet
|
|
(rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
|
|
check_rx_packet
|
|
(rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
|
|
|
|
TASKS for append and check CRC to/of TX packet:
|
|
-----------------------------------------------
|
|
append_tx_crc
|
|
(txpnt_wb[31:0], len[15:0], negated_crc);
|
|
check_tx_crc
|
|
(txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
|
|
|
|
TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
|
|
--------------------------------------------------------------------------------
|
|
append_rx_crc
|
|
(rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
|
|
*/
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// test_mac_half_duplex_flow: ////
|
|
//// ////
|
|
//// 0: Test ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
|
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
|
begin
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test collision and late collision while transmitting and ////
|
|
//// receiving normal frames. Using 4 TX and RX buffer ////
|
|
//// decriptors ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 0) //
|
|
begin
|
|
// TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )
|
|
//
|
|
test_name = "TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )";
|
|
`TIME; $display(" TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )");
|
|
|
|
// reset MAC completely
|
////////////////////////////////////////////////////////////////////
|
hard_reset;
|
//// ////
|
// set wb slave response
|
//// Receive control frames with PASSALL option turned off ////
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
//// Using only one RX buffer decriptor ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 4) //
|
|
begin
|
|
// TEST 4: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )
|
|
test_name = "TEST 4: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )";
|
|
`TIME; $display(" TEST 4: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )");
|
|
|
max_tmp = 0;
|
// unmask interrupts
|
min_tmp = 0;
|
|
// set 4 TX buffer descriptors (4 TX and 4 RX BDs will be used) - must be set before TX/RX enable
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
// enable TX and RX, set half-duplex mode, receive small, NO correct IFG
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_RXEN | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare two packets of MAXFL length for TX and RX
|
// prepare one control (PAUSE)packet
|
wait (wbm_working == 0);
|
st_data = 8'h00;
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
set_rx_packet(0, 60, 1'b0, 48'h0180_c200_0001, 48'h0708_090A_0B0C, 16'h8808, st_data); // length without CRC
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
// prepare one packet of 100 bytes long
|
min_tmp = tmp[31:16];
|
st_data = 8'h1A;
|
st_data = 8'h17;
|
set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet(0, (min_tmp), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, (min_tmp), 1'b0, 1'b0);
|
|
st_data = 8'h92;
|
|
set_tx_packet(`MEMORY_BASE, (min_tmp), st_data); // length without CRC
|
|
append_tx_crc (`MEMORY_BASE, (min_tmp), 1'b0);
|
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 10;
|
|
|
// set TX and RX Buffer Descriptors
|
for (i=0; i<4; i=i+1)
|
tx_bd_num = 0; // tx BDs go from 0 to 3
|
|
rx_bd_num = 4; // rx BDs go from 4 to 7
|
|
set_tx_bd(0, 3, i_length[15:0], 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
|
|
set_tx_bd_wrap(3);
|
|
set_rx_bd(4, 7, 1'b1, `MEMORY_BASE);
|
|
set_rx_bd_wrap(7);
|
|
set_rx_bd_empty(4, 7);
|
|
|
|
// frame_ended = 0;
|
|
tmp_len = 0;
|
|
num_of_frames = 0;// 0; // 10;
|
|
num_of_iter = 0;
|
|
// num_of_bd = 0;
|
|
// i_length = 0;// (0 - 4); // 6; // 4 less due to CRC
|
|
while (num_of_frames < 80)
|
|
begin
|
begin
|
// change COLLVALID bits in COLLCONF register
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
if ((num_of_frames == 0) && (num_of_iter == 0))
|
case (i)
|
|
0: // Interrupt is generated
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i));
|
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
tmp[5:0] = 6'h00; // 6'b00_0000 -> 0 + 1 = 1 byte from preamble
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wait (wbm_working == 0);
|
// not detect carrier sense in FD and no collision
|
wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
$display(" Collision window is set to 1 byte after preamble and SFD");
|
eth_phy.collision(0);
|
end
|
end
|
else if ((num_of_frames == 0) && (num_of_iter == 1))
|
1: // Interrupt is not generated
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i) + 64));
|
|
// mask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
tmp[5:0] = 6'h15; // 6'b01_0101 -> 21 + 1 = 22 bytes from preamble
|
// detect carrier sense in FD and no collision
|
wait (wbm_working == 0);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
eth_phy.collision(0);
|
$display(" Collision window is set to 22 bytes after preamble and SFD");
|
|
end
|
end
|
else if ((num_of_frames == 0) && (num_of_iter == 2))
|
2: // Interrupt is not generated
|
begin
|
begin
|
|
// disable interrupt generation
|
|
set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i));
|
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
tmp[5:0] = 6'h2A; // 6'b10_1010 -> 42 + 1 = 43 bytes from preamble
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wait (wbm_working == 0);
|
// not detect carrier sense in FD and set collision
|
wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
$display(" Collision window is set to 43 bytes after preamble and SFD");
|
eth_phy.collision(1);
|
end
|
end
|
else if ((num_of_frames == 0) && (num_of_iter == 3))
|
default: // 3: // Interrupt is not generated
|
begin
|
begin
|
|
// disable interrupt generation
|
|
set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i) + 64));
|
|
// mask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
tmp[5:0] = 6'h3F; // 6'b11_1111 -> 63 + 1 = 64 bytes from preamble
|
// detect carrier sense in FD and set collision
|
wait (wbm_working == 0);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
eth_phy.collision(1);
|
$display(" Collision window is set to 64 bytes after preamble and SFD");
|
|
end
|
end
|
|
endcase
|
|
|
|
append_rx_crc (64, 100, 1'b0, 1'b0); // To the second (data) packet
|
//wire MRxDV; // This goes to PHY
|
// set wrap bit
|
//wire MRxErr; // This goes to PHY
|
set_rx_bd_wrap(127);
|
//wire MColl; // This goes to PHY
|
set_rx_bd_empty(127, 127);
|
//wire MCrs; // This goes to PHY
|
|
//wire MTxEn;
|
|
//wire MTxErr;
|
|
// CHECK END OF RECEIVE WHILE TRANSMITTING
|
|
frame_ended = 0;
|
|
check_rx_frame = 0;
|
|
fork
|
fork
|
// send frames
|
|
begin // start with RX frame
|
|
repeat(num_of_frames) @(posedge mrx_clk);
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (min_tmp + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin // start with TX frame
|
|
repeat(2) @(posedge mrx_clk);
|
|
repeat(2) @(posedge wb_clk);
|
|
#1 set_tx_bd_ready(tx_bd_num, tx_bd_num);
|
|
end
|
|
// observe TX Enable, Carrier Sense and Collision - TX frame is not repeated after Late Collision
|
|
begin
|
begin
|
wait (MCrs || MTxEn);
|
if (i[0] == 1'b0)
|
#1;
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
|
if ((MCrs == 1'b1) && (MTxEn == 1'b0)) // defer TX due to Carrier Sense
|
|
wait_for_tx_frame = 1'b1; // wait for retransmission of TX frame
|
|
else
|
else
|
begin
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 64, 104, 1'b0);
|
i = 0;
|
|
while (MColl == 1'b0) // wait for Collision to occure
|
|
begin
|
|
repeat(2) @(posedge mtx_clk); // counting bytes
|
|
#1 i = i + 1'b1;
|
|
end
|
|
i = i - 8; // subtract preamble and SFD (bytes) - Late Collision is measured from SFD!
|
|
tmp_len = eth_phy.tx_len; // without preamble and SFD (bytes)
|
|
//wait (MTxEn == 1'b0); // wait for TX frame to end
|
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
repeat(8) @(posedge wb_clk);
|
$display("1111");
|
#1 check_tx_bd(tx_bd_num, data);
|
|
if (data[15] === 0) // if transmit is aborted, then it was Late Collision
|
|
begin
|
|
wait_for_tx_frame = 1'b0; // don't wait for retransmission of TX frame
|
|
$display(" ->Late Collision occured on %0d. byte after frame and SFD", i);
|
|
end
|
|
else
|
|
wait_for_tx_frame = 1'b1; // wait for retransmission of TX frame
|
|
end
|
|
end
|
end
|
// check if RX frame is accepted
|
|
begin
|
|
wait (MRxDV === 1'b1); // start receive
|
|
wait (MRxDV === 1'b0); // end receive
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(8) @(posedge wb_clk);
|
|
#1 check_rx_bd(rx_bd_num, data);
|
|
if (data[15] === 0)
|
|
begin
|
begin
|
check_rx_frame = 1'b1; // RX frame accepted and must be checked
|
#1 check_rx_bd(127, data);
|
if ((i + 8) == 0) // add preamble and SFD length (bytes)
|
$display("aaaa");
|
$display(" ->RX frame, which started before or at beginning of TX frame, was accepted");
|
wait (MRxDV === 1'b1); // start transmit
|
else
|
$display("bbbb");
|
$display(" ->RX frame, which started %0d byte(s) after beginning of TX frame, was accepted", (i + 8));
|
#1 check_rx_bd(127, data);
|
end
|
if (data[15] !== 1)
|
else
|
|
check_rx_frame = 1'b0; // RX frame rejected
|
|
repeat(1) @(posedge wb_clk);
|
|
end
|
|
join
|
|
|
|
|
|
|
|
// check length of a PACKET
|
|
if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
|
|
((data[31:16] != 0) && (num_of_frames < 3)) )
|
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check received RX packet data and CRC
|
wait (MRxDV === 1'b0); // end transmit
|
//if ((num_of_frames == 5))
|
$display("cccc");
|
//begin // CRC has 4 bytes for itself
|
while (data[15] === 1)
|
// if (i_length[0] == 1'b1)
|
begin
|
// begin
|
#1 check_rx_bd(127, data);
|
// check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
@(posedge wb_clk);
|
// end
|
end
|
// else
|
repeat (1) @(posedge wb_clk);
|
// begin
|
$display("2222");
|
// check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
|
end
|
// end
|
join
|
// if (tmp > 0)
|
$display("dddd");
|
// begin
|
// check length of a PACKET
|
// `TIME; $display("*E Wrong data of the received packet");
|
if (data[31:16] != (i_length + 4))
|
// test_fail("Wrong data of the received packet");
|
begin
|
// fail = fail + 1;
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
// end
|
data[31:16], (i_length + 4));
|
//end
|
test_fail("Wrong length of the packet out from PHY");
|
//else
|
fail = fail + 1;
|
//if ((num_of_frames == 10))
|
end
|
//begin // CRC has 4 bytes for itself
|
// checking in the following if statement is performed only for first and last 64 lengths
|
// if (i_length[0] == 1'b1)
|
// check received RX packet data and CRC
|
// begin
|
|
// check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
|
// end
|
|
// else
|
|
// begin
|
|
// check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
|
|
// end
|
|
// if (tmp > 0)
|
|
// begin
|
|
// `TIME; $display("*E Wrong data of the received packet");
|
|
// test_fail("Wrong data of the received packet");
|
|
// fail = fail + 1;
|
|
// end
|
|
//end
|
|
//else
|
|
if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
|
|
begin // CRC has 4 bytes for itself
|
|
if (i_length[0] == 1'b0)
|
if (i_length[0] == 1'b0)
|
begin
|
begin
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
end
|
end
|
else
|
else
|
| Line 17244... |
Line 20598... |
begin
|
begin
|
`TIME; $display("*E Wrong data of the received packet");
|
`TIME; $display("*E Wrong data of the received packet");
|
test_fail("Wrong data of the received packet");
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (num_of_frames >= 3) // Frames smaller than 3 are not received.
|
if (i_length[1:0] == 2'h0)
|
begin // Frames greater then 5 always cause an interrupt (Frame received)
|
begin
|
if (wb_int !== 1'b1) // Frames with length 3 or 4 always cause an interrupt (CRC error)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 17265... |
Line 20617... |
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (num_of_frames >= min_tmp)
|
check_rx_bd(127, data);
|
begin
|
if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
|
if ( (data[15:0] !== 16'h6000) && // wrap bit
|
|
(data[15:0] !== 16'h4000) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames > 4)
|
|
begin
|
|
if ( (data[15:0] !== 16'h6004) && // wrap bit
|
|
(data[15:0] !== 16'h4004) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames > 2)
|
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6006) && // wrap bit
|
if ( ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b0)) ||
|
(data[15:0] !== 16'h4006) ) // without wrap bit
|
((data[15:0] !== 16'h6000) && (i_length[0] == 1'b1)) )
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else
|
else // interrupt not enabled
|
begin
|
begin
|
if (data[15] !== 1'b1)
|
if ( ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b0)) ||
|
|
((data[15:0] !== 16'h2000) && (i_length[0] == 1'b1)) )
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
|
// clear RX buffer descriptor for first 4 frames
|
|
if (i_length < min_tmp)
|
|
clear_rx_bd(127, 127);
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (num_of_frames >= 5)
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
begin
|
begin
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Receive Buffer was not set");
|
test_fail("Interrupt Receive Buffer was not set");
|
| Line 17324... |
Line 20660... |
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
|
|
begin
|
|
if (data) // Checking if any interrupt is pending)
|
|
begin
|
|
`TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
|
|
test_fail("Interrupts were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
else
|
begin
|
begin
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
if (data !== 0)
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 17358... |
Line 20679... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (num_of_frames == 3)
|
if ((i_length + 4) == (min_tmp + 64))
|
begin
|
|
$display(" using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
|
|
$display(" ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
|
|
0, 3);
|
|
end
|
|
else if (num_of_frames == 9)
|
|
begin
|
|
$display(" using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
|
|
$display(" ->packet with length 4 is not received (length increasing by 1 byte)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
5, 9);
|
|
end
|
|
else if (num_of_frames == 17)
|
|
begin
|
|
$display(" using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
10, 17);
|
|
end
|
|
else if (num_of_frames == 27)
|
|
begin
|
|
$display(" using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
18, 27);
|
|
end
|
|
else if (num_of_frames == 40)
|
|
begin
|
|
$display(" using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
28, 40);
|
|
end
|
|
else if (num_of_frames == 54)
|
|
begin
|
begin
|
$display(" using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
|
// starting length is min_tmp, ending length is (min_tmp + 64)
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
$display(" receive small packets is NOT selected");
|
41, 54);
|
$display(" ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
|
min_tmp, (min_tmp + 64));
|
|
// set receive small, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if (num_of_frames == 69)
|
else if ((i_length + 4) == (max_tmp - 16))
|
begin
|
begin
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
$display(" receive small packets is selected");
|
55, 69);
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
|
(min_tmp + 64 + 128), tmp_data);
|
|
// reset receive small, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if (num_of_frames == 69)
|
else if ((i_length + 4) == max_tmp)
|
begin
|
begin
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
$display(" receive small packets is NOT selected");
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
$display(" ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
55, 69);
|
(max_tmp - (4 + 16)), max_tmp);
|
end
|
end
|
else if (num_of_frames == 77)
|
// set length (loop variable)
|
|
if ((i_length + 4) < (min_tmp + 64))
|
|
i_length = i_length + 1;
|
|
else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
|
begin
|
begin
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
i_length = i_length + 128;
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
70, 77);
|
|
end
|
end
|
// set length (loop variable)
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
|
i_length = max_tmp - (4 + 16);
|
|
else if ((i_length + 4) >= (max_tmp - 16))
|
i_length = i_length + 1;
|
i_length = i_length + 1;
|
// the number of frame transmitted
|
|
num_of_frames = num_of_frames + 1;
|
|
if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
|
|
(num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
|
|
(num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
|
|
(num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
|
|
num_of_bd = 120;
|
|
else
|
else
|
num_of_bd = num_of_bd + 1;
|
begin
|
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
|
#10 $stop;
|
|
end
|
end
|
end
|
// disable RX
|
// disable RX
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
@(posedge wb_clk);
|
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Receive control frames with PASSALL option turned off ////
|
//// Receive control frames with PASSALL option turned off ////
|
//// Using only one RX buffer decriptor ( 10Mbps ). ////
|
//// Using only one RX buffer decriptor ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) //
|
if (test_num == 5) //
|
begin
|
begin
|
// TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )
|
// TEST 5: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 100Mbps )
|
test_name = "TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )";
|
test_name = "TEST 5: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 100Mbps )";
|
`TIME; $display(" TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )");
|
`TIME; $display(" TEST 5: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 100Mbps )");
|
|
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 17474... |
Line 20776... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 100;
|
|
|
for (i=0; i<4; i=i+1)
|
for (i=0; i<4; i=i+1)
|
begin
|
begin
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
case (i)
|
case (i)
|
| Line 17732... |
Line 21034... |
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
end
|
|
|
|
|
end
|
end
|
endtask // test_mac_half_duplex_flow
|
endtask // test_mac_half_duplex_flow
|
|
|
|
|
| Line 17863... |
Line 21164... |
repeat(2) @(posedge wb_clk);
|
repeat(2) @(posedge wb_clk);
|
#2 wb_rst = 1'b0;
|
#2 wb_rst = 1'b0;
|
end
|
end
|
endtask // hard_reset
|
endtask // hard_reset
|
|
|
task reset_mac; // MAC module
|
|
reg [31:0] tmp;
|
|
reg [31:0] tmp_no_rst;
|
|
begin
|
|
// read MODER register first
|
|
wbm_read(`ETH_MODER, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set reset bit - write back to MODER register with RESET bit
|
|
wbm_write(`ETH_MODER, (`ETH_MODER_RST | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// clear reset bit - write back to MODER register without RESET bit
|
|
tmp_no_rst = `ETH_MODER_RST;
|
|
tmp_no_rst = ~tmp_no_rst;
|
|
wbm_write(`ETH_MODER, (tmp_no_rst & tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
endtask // reset_mac
|
|
|
|
task set_tx_bd;
|
task set_tx_bd;
|
input [6:0] tx_bd_num_start;
|
input [6:0] tx_bd_num_start;
|
input [6:0] tx_bd_num_end;
|
input [6:0] tx_bd_num_end;
|
input [15:0] len;
|
input [15:0] len;
|
input irq;
|
input irq;
|
| Line 17897... |
Line 21183... |
begin
|
begin
|
// buf_addr = `TX_BUF_BASE + i * 32'h600;
|
// buf_addr = `TX_BUF_BASE + i * 32'h600;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_ptr_addr = bd_status_addr + 4;
|
bd_ptr_addr = bd_status_addr + 4;
|
// initialize BD - status
|
// initialize BD - status
|
|
wait (wbm_working == 0);
|
wbm_write(bd_status_addr, {len, 1'b0, irq, 1'b0, pad, crc, 11'h0},
|
wbm_write(bd_status_addr, {len, 1'b0, irq, 1'b0, pad, crc, 11'h0},
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
|
// initialize BD - pointer
|
// initialize BD - pointer
|
|
wait (wbm_working == 0);
|
wbm_write(bd_ptr_addr, txpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
|
wbm_write(bd_ptr_addr, txpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
|
end
|
end
|
end
|
end
|
endtask // set_tx_bd
|
endtask // set_tx_bd
|
|
|
task set_tx_bd_wrap;
|
task set_tx_bd_wrap;
|
input [6:0] tx_bd_num_end;
|
input [6:0] tx_bd_num_end;
|
integer bd_status_addr, tmp;
|
integer bd_status_addr, tmp;
|
begin
|
begin
|
bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
|
bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
|
|
wait (wbm_working == 0);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set wrap bit to this BD - this BD should be last-one
|
// set wrap bit to this BD - this BD should be last-one
|
|
wait (wbm_working == 0);
|
wbm_write(bd_status_addr, (`ETH_TX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(bd_status_addr, (`ETH_TX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
endtask // set_tx_bd_wrap
|
endtask // set_tx_bd_wrap
|
|
|
task set_tx_bd_ready;
|
task set_tx_bd_ready;
|
| Line 17925... |
Line 21215... |
integer bd_status_addr, tmp;
|
integer bd_status_addr, tmp;
|
begin
|
begin
|
for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
|
for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
|
begin
|
begin
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
|
wait (wbm_working == 0);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set empty bit to this BD - this BD should be ready
|
// set empty bit to this BD - this BD should be ready
|
|
wait (wbm_working == 0);
|
wbm_write(bd_status_addr, (`ETH_TX_BD_READY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(bd_status_addr, (`ETH_TX_BD_READY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
end
|
end
|
endtask // set_tx_bd_ready
|
endtask // set_tx_bd_ready
|
|
|
| Line 17938... |
Line 21230... |
input [6:0] tx_bd_num_end;
|
input [6:0] tx_bd_num_end;
|
output [31:0] tx_bd_status;
|
output [31:0] tx_bd_status;
|
integer bd_status_addr, tmp;
|
integer bd_status_addr, tmp;
|
begin
|
begin
|
bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
|
bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
|
|
wait (wbm_working == 0);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
tx_bd_status = tmp;
|
tx_bd_status = tmp;
|
end
|
end
|
endtask // check_tx_bd
|
endtask // check_tx_bd
|
|
|
| Line 17954... |
Line 21247... |
for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
|
for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
|
begin
|
begin
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_ptr_addr = bd_status_addr + 4;
|
bd_ptr_addr = bd_status_addr + 4;
|
// clear BD - status
|
// clear BD - status
|
|
wait (wbm_working == 0);
|
wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// clear BD - pointer
|
// clear BD - pointer
|
|
wait (wbm_working == 0);
|
wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
end
|
end
|
endtask // clear_tx_bd
|
endtask // clear_tx_bd
|
|
|
| Line 17980... |
Line 21275... |
// bd_ptr_addr = bd_status_addr + 4;
|
// bd_ptr_addr = bd_status_addr + 4;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_ptr_addr = bd_status_addr + 4;
|
bd_ptr_addr = bd_status_addr + 4;
|
|
|
// initialize BD - status
|
// initialize BD - status
|
|
wait (wbm_working == 0);
|
// wbm_write(bd_status_addr, 32'h0000c000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
|
// wbm_write(bd_status_addr, 32'h0000c000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
|
wbm_write(bd_status_addr, {17'h0, irq, 14'h0},
|
wbm_write(bd_status_addr, {17'h0, irq, 14'h0},
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// initialize BD - pointer
|
// initialize BD - pointer
|
|
wait (wbm_working == 0);
|
// wbm_write(bd_ptr_addr, buf_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
|
// wbm_write(bd_ptr_addr, buf_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
|
wbm_write(bd_ptr_addr, rxpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
|
wbm_write(bd_ptr_addr, rxpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
|
end
|
end
|
end
|
end
|
endtask // set_rx_bd
|
endtask // set_rx_bd
|
| Line 17996... |
Line 21293... |
input [6:0] rx_bd_num_end;
|
input [6:0] rx_bd_num_end;
|
integer bd_status_addr, tmp;
|
integer bd_status_addr, tmp;
|
begin
|
begin
|
// bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
|
// bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
|
bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
|
bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
|
|
wait (wbm_working == 0);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set wrap bit to this BD - this BD should be last-one
|
// set wrap bit to this BD - this BD should be last-one
|
|
wait (wbm_working == 0);
|
wbm_write(bd_status_addr, (`ETH_RX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(bd_status_addr, (`ETH_RX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
endtask // set_rx_bd_wrap
|
endtask // set_rx_bd_wrap
|
|
|
task set_rx_bd_empty;
|
task set_rx_bd_empty;
|
| Line 18012... |
Line 21311... |
begin
|
begin
|
for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
|
for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
|
begin
|
begin
|
// bd_status_addr = `RX_BD_BASE + i * 8;
|
// bd_status_addr = `RX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
|
wait (wbm_working == 0);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set empty bit to this BD - this BD should be ready
|
// set empty bit to this BD - this BD should be ready
|
|
wait (wbm_working == 0);
|
wbm_write(bd_status_addr, (`ETH_RX_BD_EMPTY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(bd_status_addr, (`ETH_RX_BD_EMPTY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
end
|
end
|
endtask // set_rx_bd_empty
|
endtask // set_rx_bd_empty
|
|
|
| Line 18026... |
Line 21327... |
output [31:0] rx_bd_status;
|
output [31:0] rx_bd_status;
|
integer bd_status_addr, tmp;
|
integer bd_status_addr, tmp;
|
begin
|
begin
|
// bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
|
// bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
|
bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
|
bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
|
|
wait (wbm_working == 0);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
rx_bd_status = tmp;
|
rx_bd_status = tmp;
|
end
|
end
|
endtask // check_rx_bd
|
endtask // check_rx_bd
|
|
|
| Line 18043... |
Line 21345... |
begin
|
begin
|
// bd_status_addr = `RX_BD_BASE + i * 8;
|
// bd_status_addr = `RX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_ptr_addr = bd_status_addr + 4;
|
bd_ptr_addr = bd_status_addr + 4;
|
// clear BD - status
|
// clear BD - status
|
|
wait (wbm_working == 0);
|
wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// clear BD - pointer
|
// clear BD - pointer
|
|
wait (wbm_working == 0);
|
wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
end
|
end
|
endtask // clear_rx_bd
|
endtask // clear_rx_bd
|
|
|
| Line 18141... |
Line 21445... |
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 1];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 1];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 2];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 2];
|
i = 3;
|
i = 3;
|
if (data_phy[23:0] !== data_wb[23:0])
|
if (data_phy[23:0] !== data_wb[23:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong 1. word (3 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[23:0], data_wb[23:0]);
|
//$display("*E Wrong 1. word (3 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[23:0], data_wb[23:0]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
//$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
failure = 1;
|
failure = 1;
|
end
|
end
|
end
|
end
|
else if (addr_wb[1:0] == 2)
|
else if (addr_wb[1:0] == 2)
|
begin
|
begin
|
| Line 18156... |
Line 21460... |
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0]];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0]];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 1];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 1];
|
i = 2;
|
i = 2;
|
if (data_phy[15:0] !== data_wb[15:0])
|
if (data_phy[15:0] !== data_wb[15:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong 1. word (2 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[15:0], data_wb[15:0]);
|
//$display("*E Wrong 1. word (2 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[15:0], data_wb[15:0]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
//$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
failure = 1;
|
failure = 1;
|
end
|
end
|
end
|
end
|
else if (addr_wb[1:0] == 3)
|
else if (addr_wb[1:0] == 3)
|
begin
|
begin
|
| Line 18170... |
Line 21474... |
data_phy[31: 8] = 0;
|
data_phy[31: 8] = 0;
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0]];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0]];
|
i = 1;
|
i = 1;
|
if (data_phy[7:0] !== data_wb[7:0])
|
if (data_phy[7:0] !== data_wb[7:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong 1. word (1 byte) of TX packet! phy: %0h, wb: %0h", data_phy[7:0], data_wb[7:0]);
|
//$display("*E Wrong 1. word (1 byte) of TX packet! phy: %0h, wb: %0h", data_phy[7:0], data_wb[7:0]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
//$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
failure = 1;
|
failure = 1;
|
end
|
end
|
end
|
end
|
else
|
else
|
i = 0;
|
i = 0;
|
| Line 18190... |
Line 21494... |
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
|
|
|
if (data_phy[31:0] !== data_wb[31:0])
|
if (data_phy[31:0] !== data_wb[31:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
//$display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
//$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
delta_t = !delta_t;
|
delta_t = !delta_t;
|
#1;
|
#1;
|
| Line 18208... |
Line 21512... |
data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
|
data_phy[ 7: 0] = 0;
|
data_phy[ 7: 0] = 0;
|
if (data_phy[31:8] !== data_wb[31:8])
|
if (data_phy[31:8] !== data_wb[31:8])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %d. word (3 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
|
//$display("*E Wrong %d. word (3 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
//$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
else if((len - i) == 2)
|
else if((len - i) == 2)
|
begin
|
begin
|
| Line 18223... |
Line 21527... |
data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
|
data_phy[15: 8] = 0;
|
data_phy[15: 8] = 0;
|
data_phy[ 7: 0] = 0;
|
data_phy[ 7: 0] = 0;
|
if (data_phy[31:16] !== data_wb[31:16])
|
if (data_phy[31:16] !== data_wb[31:16])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %d. word (2 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
|
//$display("*E Wrong %d. word (2 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
//$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
else if((len - i) == 1)
|
else if((len - i) == 1)
|
begin
|
begin
|
| Line 18238... |
Line 21542... |
data_phy[23:16] = 0;
|
data_phy[23:16] = 0;
|
data_phy[15: 8] = 0;
|
data_phy[15: 8] = 0;
|
data_phy[ 7: 0] = 0;
|
data_phy[ 7: 0] = 0;
|
if (data_phy[31:24] !== data_wb[31:24])
|
if (data_phy[31:24] !== data_wb[31:24])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %d. word (1 byte) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
|
//$display("*E Wrong %d. word (1 byte) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
//$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
else if((len - i) == 4)
|
else if((len - i) == 4)
|
begin
|
begin
|
| Line 18253... |
Line 21557... |
data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
|
data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
|
data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
|
if (data_phy[31:0] !== data_wb[31:0])
|
if (data_phy[31:0] !== data_wb[31:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
//$display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
//$display(" address phy: %0h, address wb: %0h", addr_phy, addr_wb);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
else
|
else
|
$display("(%0t)(%m) ERROR", $time);
|
$display("(%0t)(%m) ERROR", $time);
|
| Line 18435... |
Line 21739... |
failure = 0;
|
failure = 0;
|
|
|
// First write might not be word allign.
|
// First write might not be word allign.
|
if(addr_wb[1:0] == 1)
|
if(addr_wb[1:0] == 1)
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb - 1, data_wb, 4'h7);
|
wb_slave.rd_mem(addr_wb[21:0] - 1, data_wb, 4'h7);
|
data_phy[31:24] = 0;
|
data_phy[31:24] = 0;
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0]];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0]];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + 1];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + 1];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 2];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 2];
|
i = 3;
|
i = 3;
|
if (data_phy[23:0] !== data_wb[23:0])
|
if (data_phy[23:0] !== data_wb[23:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
|
//$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
|
$display("*E Wrong 1. word (3 bytes) of RX packet! phy = %h, wb = %h", data_phy[23:0], data_wb[23:0]);
|
//$display("*E Wrong 1. word (3 bytes) of RX packet! phy = %h, wb = %h", data_phy[23:0], data_wb[23:0]);
|
failure = 1;
|
failure = 1;
|
end
|
end
|
end
|
end
|
else if (addr_wb[1:0] == 2)
|
else if (addr_wb[1:0] == 2)
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb - 2, data_wb, 4'h3);
|
wb_slave.rd_mem(addr_wb[21:0] - 2, data_wb, 4'h3);
|
data_phy[31:16] = 0;
|
data_phy[31:16] = 0;
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0]];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0]];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 1];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 1];
|
i = 2;
|
i = 2;
|
if (data_phy[15:0] !== data_wb[15:0])
|
if (data_phy[15:0] !== data_wb[15:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
|
//$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
|
$display("*E Wrong 1. word (2 bytes) of RX packet! phy = %h, wb = %h", data_phy[15:0], data_wb[15:0]);
|
//$display("*E Wrong 1. word (2 bytes) of RX packet! phy = %h, wb = %h", data_phy[15:0], data_wb[15:0]);
|
failure = 1;
|
failure = 1;
|
end
|
end
|
end
|
end
|
else if (addr_wb[1:0] == 3)
|
else if (addr_wb[1:0] == 3)
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb - 3, data_wb, 4'h1);
|
wb_slave.rd_mem(addr_wb[21:0] - 3, data_wb, 4'h1);
|
data_phy[31: 8] = 0;
|
data_phy[31: 8] = 0;
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0]];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0]];
|
i = 1;
|
i = 1;
|
if (data_phy[7:0] !== data_wb[7:0])
|
if (data_phy[7:0] !== data_wb[7:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
|
//$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
|
$display("*E Wrong 1. word (1 byte) of RX packet! phy = %h, wb = %h", data_phy[7:0], data_wb[7:0]);
|
//$display("*E Wrong 1. word (1 byte) of RX packet! phy = %h, wb = %h", data_phy[7:0], data_wb[7:0]);
|
failure = 1;
|
failure = 1;
|
end
|
end
|
end
|
end
|
else
|
else
|
i = 0;
|
i = 0;
|
delta_t = !delta_t;
|
delta_t = !delta_t;
|
|
|
for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
|
for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
|
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hF);
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
|
if (data_phy[31:0] !== data_wb[31:0])
|
if (data_phy[31:0] !== data_wb[31:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
if (i == 0)
|
//if (i == 0)
|
$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
|
// $display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
|
$display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
//$display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
delta_t = !delta_t;
|
delta_t = !delta_t;
|
|
|
// Last word
|
// Last word
|
if((len - i) == 3)
|
if((len - i) == 3)
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
|
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hF);
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
|
if (plus_dribble_nibble)
|
if (plus_dribble_nibble)
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
|
else
|
else
|
data_phy[ 7: 0] = 0;
|
data_phy[ 7: 0] = 0;
|
if (data_phy[31:8] !== data_wb[31:8])
|
if (data_phy[31:8] !== data_wb[31:8])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %0d. word (3 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
|
//$display("*E Wrong %0d. word (3 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
if (plus_dribble_nibble && successful_dribble_nibble)
|
if (plus_dribble_nibble && successful_dribble_nibble)
|
begin
|
begin
|
if (data_phy[3:0] !== data_wb[3:0])
|
if (data_phy[3:0] !== data_wb[3:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
|
//$display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
else if (plus_dribble_nibble && !successful_dribble_nibble)
|
else if (plus_dribble_nibble && !successful_dribble_nibble)
|
begin
|
begin
|
if (data_phy[3:0] === data_wb[3:0])
|
if (data_phy[3:0] === data_wb[3:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
|
//$display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
else if((len - i) == 2)
|
else if((len - i) == 2)
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb + i, data_wb, 4'hE);
|
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hE);
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
if (plus_dribble_nibble)
|
if (plus_dribble_nibble)
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
|
else
|
else
|
data_phy[15: 8] = 0;
|
data_phy[15: 8] = 0;
|
data_phy[ 7: 0] = 0;
|
data_phy[ 7: 0] = 0;
|
if (data_phy[31:16] !== data_wb[31:16])
|
if (data_phy[31:16] !== data_wb[31:16])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %0d. word (2 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
|
//$display("*E Wrong %0d. word (2 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
if (plus_dribble_nibble && successful_dribble_nibble)
|
if (plus_dribble_nibble && successful_dribble_nibble)
|
begin
|
begin
|
if (data_phy[11:8] !== data_wb[11:8])
|
if (data_phy[11:8] !== data_wb[11:8])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
|
//$display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
else if (plus_dribble_nibble && !successful_dribble_nibble)
|
else if (plus_dribble_nibble && !successful_dribble_nibble)
|
begin
|
begin
|
if (data_phy[11:8] === data_wb[11:8])
|
if (data_phy[11:8] === data_wb[11:8])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
|
//$display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
else if((len - i) == 1)
|
else if((len - i) == 1)
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb + i, data_wb, 4'hC);
|
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hC);
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
if (plus_dribble_nibble)
|
if (plus_dribble_nibble)
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
else
|
else
|
data_phy[23:16] = 0;
|
data_phy[23:16] = 0;
|
data_phy[15: 8] = 0;
|
data_phy[15: 8] = 0;
|
data_phy[ 7: 0] = 0;
|
data_phy[ 7: 0] = 0;
|
if (data_phy[31:24] !== data_wb[31:24])
|
if (data_phy[31:24] !== data_wb[31:24])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %0d. word (1 byte) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
|
//$display("*E Wrong %0d. word (1 byte) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
if (plus_dribble_nibble && successful_dribble_nibble)
|
if (plus_dribble_nibble && successful_dribble_nibble)
|
begin
|
begin
|
if (data_phy[19:16] !== data_wb[19:16])
|
if (data_phy[19:16] !== data_wb[19:16])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
|
//$display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
else if (plus_dribble_nibble && !successful_dribble_nibble)
|
else if (plus_dribble_nibble && !successful_dribble_nibble)
|
begin
|
begin
|
if (data_phy[19:16] === data_wb[19:16])
|
if (data_phy[19:16] === data_wb[19:16])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
|
//$display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
else if((len - i) == 4)
|
else if((len - i) == 4)
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
|
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hF);
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
|
data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
|
data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
|
if (data_phy[31:0] !== data_wb[31:0])
|
if (data_phy[31:0] !== data_wb[31:0])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
//$display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
if (plus_dribble_nibble)
|
if (plus_dribble_nibble)
|
begin
|
begin
|
wb_slave.rd_mem(addr_wb + i + 4, data_wb, 4'h8);
|
wb_slave.rd_mem(addr_wb[21:0] + i + 4, data_wb, 4'h8);
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i + 4];
|
data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i + 4];
|
if (successful_dribble_nibble)
|
if (successful_dribble_nibble)
|
begin
|
begin
|
if (data_phy[27:24] !== data_wb[27:24])
|
if (data_phy[27:24] !== data_wb[27:24])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
|
//$display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (data_phy[27:24] === data_wb[27:24])
|
if (data_phy[27:24] === data_wb[27:24])
|
begin
|
begin
|
`TIME;
|
//`TIME;
|
$display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
|
//$display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
|
failure = failure + 1;
|
failure = failure + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 19531... |
Line 22835... |
|
|
//////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////
|
// MIIM Basic tasks
|
// MIIM Basic tasks
|
//////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////
|
|
|
task reset_mii; // MII module
|
|
reg [31:0] tmp;
|
|
reg [31:0] tmp_no_rst;
|
|
begin
|
|
// read MII mode register first
|
|
wbm_read(`ETH_MIIMODER, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set reset bit - write back to MII mode register with RESET bit
|
|
wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_RST | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// clear reset bit - write back to MII mode register without RESET bit
|
|
tmp_no_rst = `ETH_MIIMODER_RST;
|
|
tmp_no_rst = ~tmp_no_rst;
|
|
wbm_write(`ETH_MIIMODER, (tmp_no_rst & tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
endtask // reset_mii
|
|
|
|
task mii_set_clk_div; // set clock divider for MII clock
|
task mii_set_clk_div; // set clock divider for MII clock
|
input [7:0] clk_div;
|
input [7:0] clk_div;
|
begin
|
begin
|
// MII mode register
|
// MII mode register
|
wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_CLKDIV & clk_div), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_CLKDIV & clk_div), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
