| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.32 2004/03/26 15:59:21 tadejm
|
|
// Latest Ethernet IP core testbench.
|
|
//
|
// Revision 1.31 2003/12/05 12:46:26 tadejm
|
// Revision 1.31 2003/12/05 12:46:26 tadejm
|
// Updated testbench. Some more testcases, some repaired.
|
// Updated testbench. Some more testcases, some repaired.
|
//
|
//
|
// Revision 1.30 2003/10/17 07:45:17 markom
|
// Revision 1.30 2003/10/17 07:45:17 markom
|
// mbist signals updated according to newest convention
|
// mbist signals updated according to newest convention
|
| Line 467... |
Line 470... |
integer tests_failed;
|
integer tests_failed;
|
reg [799:0] test_name; // used for tb_log_file
|
reg [799:0] test_name; // used for tb_log_file
|
|
|
reg [3:0] wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
|
reg [3:0] wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
|
reg [3:0] wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
|
reg [3:0] wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
|
reg [2:0] wbs_waits; // wait cycles befor WB Slave responds
|
reg [3:0] wbs_waits; // wait cycles befor WB Slave responds
|
reg [7:0] wbs_retries; // if RTY response, then this is the number of retries before ACK
|
reg [7:0] wbs_retries; // if RTY response, then this is the number of retries before ACK
|
|
|
reg wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working
|
reg wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working
|
|
|
|
|
| Line 502... |
Line 505... |
$display("===========================================================================");
|
$display("===========================================================================");
|
$display("PHY generates ideal Carrier sense and Collision signals for following tests");
|
$display("PHY generates ideal Carrier sense and Collision signals for following tests");
|
$display("===========================================================================");
|
$display("===========================================================================");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(0);
|
eth_phy.carrier_sense_real_delay(0);
|
test_mac_full_duplex_transmit(0, 21); // 0 - 21
|
test_mac_full_duplex_transmit(0, 23); // 0 - 23
|
test_mac_full_duplex_receive(0, 13); // 0 - 13
|
test_mac_full_duplex_receive(0, 15); // 0 - 15
|
test_mac_full_duplex_flow_control(0, 5); // 0 - 5
|
test_mac_full_duplex_flow_control(0, 5); // 0 - 5
|
test_mac_half_duplex_flow(0, 1);
|
test_mac_half_duplex_flow(0, 1);
|
|
|
$display("");
|
$display("");
|
$display("===========================================================================");
|
$display("===========================================================================");
|
| Line 660... |
Line 663... |
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
data = {({8{~sel[3]}}), ({8{~sel[2]}}), ({8{~sel[1]}}), ({8{~sel[0]}})};
|
data = {({8{~sel[3]}}), ({8{~sel[2]}}), ({8{~sel[1]}}), ({8{~sel[0]}})};
|
if (tmp_data !== data)
|
if (tmp_data !== data)
|
begin
|
begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail_num("Wrong data read out form register", i_addr);
|
test_fail_num("Wrong data read out from register", i_addr);
|
`TIME;
|
`TIME;
|
$display("Wrong data read out from register - addr %h, data %h, tmp_data %h, sel %b",
|
$display("Wrong data read out from register - addr %h, data %h, tmp_data %h, sel %b",
|
addr, data, tmp_data, sel);
|
addr, data, tmp_data, sel);
|
end
|
end
|
end
|
end
|
| Line 4340... |
Line 4343... |
//// ////
|
//// ////
|
//// test_mac_full_duplex_transmit: ////
|
//// test_mac_full_duplex_transmit: ////
|
//// ////
|
//// ////
|
//// 0: Test no transmit when all buffers are RX ( 10Mbps ). ////
|
//// 0: Test no transmit when all buffers are RX ( 10Mbps ). ////
|
//// 1: Test no transmit when all buffers are RX ( 100Mbps ). ////
|
//// 1: Test no transmit when all buffers are RX ( 100Mbps ). ////
|
//// 2: Test transmit packets form MINFL to MAXFL sizes at ////
|
//// 2: Test transmit packets from MINFL to MAXFL sizes at ////
|
//// one TX buffer decriptor ( 10Mbps ). ////
|
//// one TX buffer decriptor ( 10Mbps ). ////
|
//// 3: Test transmit packets form MINFL to MAXFL sizes at ////
|
//// 3: Test transmit packets from MINFL to MAXFL sizes at ////
|
//// one TX buffer decriptor ( 100Mbps ). ////
|
//// one TX buffer decriptor ( 100Mbps ). ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
begin
|
begin
|
| Line 4536... |
Line 4539... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// Test transmit packets from MINFL to MAXFL sizes at ////
|
//// one TX buffer decriptor ( 10Mbps ). ////
|
//// one TX buffer decriptor ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) //
|
if (test_num == 2) //
|
begin
|
begin
|
| Line 4850... |
Line 4853... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// Test transmit packets from MINFL to MAXFL sizes at ////
|
//// one TX buffer decriptor ( 100Mbps ). ////
|
//// one TX buffer decriptor ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) //
|
if (test_num == 3) //
|
begin
|
begin
|
| Line 5154... |
Line 5157... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// Test transmit packets from MINFL to MAXFL sizes at ////
|
//// maximum TX buffer decriptors ( 10Mbps ). ////
|
//// maximum TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 4) //
|
if (test_num == 4) //
|
begin
|
begin
|
| Line 5288... |
Line 5291... |
end
|
end
|
endcase
|
endcase
|
// set wrap bit
|
// set wrap bit
|
set_tx_bd_wrap(0);
|
set_tx_bd_wrap(0);
|
end
|
end
|
// after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
|
// after first 8 number of frames, 128 frames from TX BD 0 to 127 will be transmitted
|
else if ((num_of_frames - 8) == 0)
|
else if ((num_of_frames - 8) == 0)
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
| Line 5318... |
Line 5321... |
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
set_tx_bd_wrap(127);
|
set_tx_bd_wrap(127);
|
end
|
end
|
// after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
|
// after 128 + first 8 number of frames, 19 frames from TX BD 0 to 18 will be transmitted
|
else if ((num_of_frames - 8) == 20) // 128
|
else if ((num_of_frames - 8) == 20) // 128
|
begin
|
begin
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
| Line 5620... |
Line 5623... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test transmit packets form MINFL to MAXFL sizes at ////
|
//// Test transmit packets from MINFL to MAXFL sizes at ////
|
//// maximum TX buffer decriptors ( 100Mbps ). ////
|
//// maximum TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 5) //
|
if (test_num == 5) //
|
begin
|
begin
|
| Line 5754... |
Line 5757... |
end
|
end
|
endcase
|
endcase
|
// set wrap bit
|
// set wrap bit
|
set_tx_bd_wrap(0);
|
set_tx_bd_wrap(0);
|
end
|
end
|
// after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
|
// after first 8 number of frames, 128 frames from TX BD 0 to 127 will be transmitted
|
else if ((num_of_frames - 8) == 0)
|
else if ((num_of_frames - 8) == 0)
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
| Line 5784... |
Line 5787... |
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
set_tx_bd_wrap(127);
|
set_tx_bd_wrap(127);
|
end
|
end
|
// after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
|
// after 128 + first 8 number of frames, 19 frames from TX BD 0 to 18 will be transmitted
|
else if ((num_of_frames - 8) == 20) // 128
|
else if ((num_of_frames - 8) == 20) // 128
|
begin
|
begin
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
| Line 6086... |
Line 6089... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test transmit packets form 0 to (MINFL - 1) sizes at ////
|
//// Test transmit packets from 0 to (MINFL - 1) sizes at ////
|
//// 8 TX buffer decriptors ( 10Mbps ). ////
|
//// 8 TX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 6) //
|
if (test_num == 6) //
|
begin
|
begin
|
| Line 6569... |
Line 6572... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test transmit packets form 0 to (MINFL - 1) sizes at ////
|
//// Test transmit packets from 0 to (MINFL - 1) sizes at ////
|
//// 8 TX buffer decriptors ( 100Mbps ). ////
|
//// 8 TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 7) //
|
if (test_num == 7) //
|
begin
|
begin
|
| Line 7631... |
Line 7634... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test transmit packets (no pads) form 0 to (MINFL - 1) ////
|
//// Test transmit packets (no pads) from 0 to (MINFL - 1) ////
|
//// sizes at 8 TX buffer decriptors ( 100Mbps ). ////
|
//// sizes at 8 TX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 9) //
|
if (test_num == 9) //
|
begin
|
begin
|
| Line 11209... |
Line 11212... |
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
|
|
end
|
|
endtask // test_mac_full_duplex_transmit
|
|
|
|
|
|
task test_mac_full_duplex_receive;
|
|
input [31:0] start_task;
|
|
input [31:0] end_task;
|
|
integer bit_start_1;
|
|
integer bit_end_1;
|
|
integer bit_start_2;
|
|
integer bit_end_2;
|
|
integer num_of_reg;
|
|
integer num_of_frames;
|
|
integer num_of_bd;
|
|
integer i_addr;
|
|
integer i_data;
|
|
integer i_length;
|
|
integer tmp_len;
|
|
integer tmp_bd;
|
|
integer tmp_bd_num;
|
|
integer tmp_data;
|
|
integer tmp_ipgt;
|
|
integer test_num;
|
|
reg [31:0] tx_bd_num;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
|
|
integer i;
|
|
integer i1;
|
|
integer i2;
|
|
integer i3;
|
|
integer fail;
|
|
integer speed;
|
|
reg frame_started;
|
|
reg frame_ended;
|
|
reg wait_for_frame;
|
|
reg check_frame;
|
|
reg stop_checking_frame;
|
|
reg first_fr_received;
|
|
reg [31:0] addr;
|
|
reg [31:0] data;
|
|
reg [31:0] tmp;
|
|
reg [ 7:0] st_data;
|
|
reg [15:0] max_tmp;
|
|
reg [15:0] min_tmp;
|
|
begin
|
|
// MAC FULL DUPLEX RECEIVE TEST
|
|
test_heading("MAC FULL DUPLEX RECEIVE TEST");
|
|
$display(" ");
|
|
$display("MAC FULL DUPLEX RECEIVE TEST");
|
|
fail = 0;
|
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
/*
|
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
|
-------------------------------------------------------------------------------------
|
|
set_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
|
|
set_tx_bd_wrap
|
|
(tx_bd_num_end[6:0]);
|
|
set_tx_bd_ready
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
check_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_status[31:0]);
|
|
clear_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and control RX buffer descriptors:
|
|
------------------------------------------------
|
|
set_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
|
|
set_rx_bd_wrap
|
|
(rx_bd_num_end[6:0]);
|
|
set_rx_bd_empty
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
check_rx_bd
|
|
(rx_bd_num_end[6:0], rx_bd_status);
|
|
clear_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and check TX packets:
|
|
-----------------------------------
|
|
set_tx_packet
|
|
(txpnt[31:0], len[15:0], eth_start_data[7:0]);
|
|
check_tx_packet
|
|
(txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
|
|
|
|
TASKS for set and check RX packets:
|
|
-----------------------------------
|
|
set_rx_packet
|
|
(rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
|
|
check_rx_packet
|
|
(rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
|
|
|
|
TASKS for append and check CRC to/of TX packet:
|
|
-----------------------------------------------
|
|
append_tx_crc
|
|
(txpnt_wb[31:0], len[15:0], negated_crc);
|
|
check_tx_crc
|
|
(txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
|
|
|
|
TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
|
|
--------------------------------------------------------------------------------
|
|
append_rx_crc
|
|
(rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
|
|
*/
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// test_mac_full_duplex_receive: ////
|
|
//// ////
|
|
//// 0: Test no receive when all buffers are TX ( 10Mbps ). ////
|
|
//// 1: Test no receive when all buffers are TX ( 100Mbps ). ////
|
|
//// 2: Test receive packet synchronization with receive ////
|
|
//// disable/enable ( 10Mbps ). ////
|
|
//// 3: Test receive packet synchronization with receive ////
|
|
//// disable/enable ( 100Mbps ). ////
|
|
//// 4: Test receive packets form MINFL to MAXFL sizes at ////
|
|
//// one RX buffer decriptor ( 10Mbps ). ////
|
|
//// 5: Test receive packets form MINFL to MAXFL sizes at ////
|
|
//// one RX buffer decriptor ( 100Mbps ). ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
|
begin
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test no receive when all buffers are TX ( 10Mbps ). ////
|
//// Test transmit packets (delayed CRC) from MINFL to MAXFL ////
|
|
//// sizes at one TX buffer decriptor ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) //
|
if (test_num == 22) //
|
begin
|
begin
|
// TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
|
// TEST 22: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
|
test_name = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
|
test_name = "TEST 22: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
|
`TIME; $display(" TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
|
`TIME; $display(" TEST 22: TRANSMIT (DELAYED CRC) PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
|
|
|
// unmask interrupts
|
max_tmp = 0;
|
wait (wbm_working == 0);
|
min_tmp = 0;
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
// set one TX buffer descriptor - must be set before TX enable
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set all buffer descriptors to TX - must be set before RX enable
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
// enable TX, set full-duplex mode, NO padding and CRC appending
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// prepare two packets of MAXFL length
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
|
min_tmp = tmp[31:16];
|
|
st_data = 8'h01;
|
|
set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
|
|
st_data = 8'h10;
|
|
set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 10;
|
|
|
i = 0;
|
i_length = (min_tmp - 4);
|
while (i < 128)
|
while (i_length <= (max_tmp - 4))
|
begin
|
begin
|
for (i1 = 0; i1 <= i; i1 = i1 + 1)
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
|
case (i_length[1:0])
|
|
2'h0: // Interrupt is generated
|
begin
|
begin
|
set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
|
// enable interrupt generation
|
append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1,
|
|
wbm_init_waits, wbm_subseq_waits);
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
|
eth_phy.collision(0);
|
end
|
end
|
set_rx_bd_wrap(i);
|
2'h1: // Interrupt is not generated
|
set_rx_bd_empty(0, i);
|
|
for (i1 = 0; i1 <= i; i1 = i1 + 1)
|
|
begin
|
begin
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
|
// enable interrupt generation
|
repeat(10) @(posedge mrx_clk);
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
|
// mask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// detect carrier sense in FD and no collision
|
|
eth_phy.carrier_sense_tx_fd_detect(1);
|
|
eth_phy.collision(0);
|
end
|
end
|
@(posedge mrx_clk);
|
2'h2: // Interrupt is not generated
|
for (i2 = 0; i2 < 20; i2 = i2 + 1)
|
|
begin
|
|
check_rx_bd(0, tmp);
|
|
#1;
|
|
if (tmp[15] === 1'b0)
|
|
begin
|
begin
|
test_fail("Receive should not start at all");
|
// disable interrupt generation
|
fail = fail + 1;
|
set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
`TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// not detect carrier sense in FD and set collision
|
|
eth_phy.carrier_sense_tx_fd_detect(0);
|
|
eth_phy.collision(1);
|
end
|
end
|
if (tmp[7:0] !== 0)
|
default: // 2'h3: // Interrupt is not generated
|
begin
|
begin
|
test_fail("Receive should not be finished since it should not start at all");
|
// disable interrupt generation
|
fail = fail + 1;
|
set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
`TIME; $display("*E Receive of should not be finished since it should not start at all");
|
// mask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// detect carrier sense in FD and set collision
|
|
eth_phy.carrier_sense_tx_fd_detect(1);
|
|
eth_phy.collision(1);
|
end
|
end
|
|
endcase
|
|
eth_phy.set_tx_mem_addr(max_tmp);
|
|
// set wrap bit
|
|
set_tx_bd_wrap(0);
|
|
set_tx_bd_ready(0, 0);
|
|
#1 check_tx_bd(0, data);
|
|
|
|
|
|
if (i_length < min_tmp) // just first four
|
|
begin
|
|
while (data[15] === 1)
|
|
begin
|
|
#1 check_tx_bd(0, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
wait (wbm_working == 0);
|
repeat (1) @(posedge wb_clk);
|
wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (tmp[6:0] !== 0)
|
|
begin
|
|
test_fail("Receive should not get INT since it should not start at all");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Receive of should not get INT since it should not start at all");
|
|
end
|
end
|
clear_rx_bd(0, i);
|
else if (i_length > (max_tmp - 8)) // just last four
|
if ((i < 5) || (i > 124))
|
begin
|
i = i + 1;
|
tmp = 0;
|
else
|
wait (MTxEn === 1'b1); // start transmit
|
i = i + 120;
|
while (tmp < (i_length - 20))
|
|
begin
|
|
#1 tmp = tmp + 1;
|
|
@(posedge wb_clk);
|
|
end
|
|
#1 check_tx_bd(0, data);
|
|
while (data[15] === 1)
|
|
begin
|
|
#1 check_tx_bd(0, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
else
|
fail = 0;
|
begin
|
|
wait (MTxEn === 1'b1); // start transmit
|
|
#1 check_tx_bd(0, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
end
|
end
|
|
wait (MTxEn === 1'b0); // end transmit
|
|
while (data[15] === 1)
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test no receive when all buffers are TX ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 1) //
|
|
begin
|
begin
|
// TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
|
#1 check_tx_bd(0, data);
|
test_name = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
|
@(posedge wb_clk);
|
`TIME; $display(" TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
|
end
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
|
// unmask interrupts
|
repeat(5) @(posedge mtx_clk); // Wait some time so PHY stores the CRC
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set all buffer descriptors to TX - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 100Mbps
|
// check length of a PACKET
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
if (eth_phy.tx_len != (i_length + 4))
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
begin
|
speed = 100;
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
// checking in the following if statement is performed only for first and last 64 lengths
|
|
if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
|
|
begin
|
|
// check transmitted TX packet data
|
|
if (i_length[0] == 0)
|
|
begin
|
|
check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
|
|
end
|
|
else
|
|
begin
|
|
check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
|
|
end
|
|
if (tmp > 0)
|
|
begin
|
|
test_fail("Wrong data of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check transmited TX packet CRC
|
|
check_tx_crc_delayed(max_tmp, i_length, 1'b0, tmp); // length without CRC
|
|
|
i = 0;
|
if (tmp > 0)
|
while (i < 128)
|
|
begin
|
begin
|
for (i1 = 0; i1 <= i; i1 = i1 + 1)
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// check WB INT signal
|
|
if (i_length[1:0] == 2'h0)
|
begin
|
begin
|
set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
|
if (wb_int !== 1'b1)
|
append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
|
begin
|
set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
end
|
end
|
set_rx_bd_wrap(i);
|
end
|
set_rx_bd_empty(0, i);
|
else
|
for (i1 = 0; i1 <= i; i1 = i1 + 1)
|
|
begin
|
begin
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
|
if (wb_int !== 1'b0)
|
repeat(10) @(posedge mrx_clk);
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
end
|
end
|
@(posedge mrx_clk);
|
end
|
for (i2 = 0; i2 < 20; i2 = i2 + 1)
|
// check TX buffer descriptor of a packet
|
|
check_tx_bd(0, data);
|
|
if (i_length[1] == 1'b0) // interrupt enabled
|
begin
|
begin
|
check_rx_bd(0, tmp);
|
if (data[15:0] !== 16'h7800)
|
#1;
|
|
if (tmp[15] === 1'b0)
|
|
begin
|
begin
|
test_fail("Receive should not start at all");
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
|
|
end
|
end
|
if (tmp[7:0] !== 0)
|
end
|
|
else // interrupt not enabled
|
begin
|
begin
|
test_fail("Receive should not be finished since it should not start at all");
|
if (data[15:0] !== 16'h3800)
|
|
begin
|
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E Receive of should not be finished since it should not start at all");
|
|
end
|
end
|
@(posedge wb_clk);
|
|
end
|
end
|
|
// clear TX buffer descriptor
|
|
clear_tx_bd(0, 0);
|
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp[6:0] !== 0)
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
begin
|
begin
|
test_fail("Receive should not get INT since it should not start at all");
|
if ((data & `ETH_INT_TXB) !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Transmit Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
`TIME; $display("*E Receive of should not get INT since it should not start at all");
|
|
end
|
end
|
clear_rx_bd(0, i);
|
if ((data & (~`ETH_INT_TXB)) !== 0)
|
if ((i < 5) || (i > 124))
|
begin
|
i = i + 1;
|
`TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
else
|
else
|
i = i + 120;
|
begin
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Transmit Buffer) was set");
|
|
fail = fail + 1;
|
end
|
end
|
// disable RX
|
end
|
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// INTERMEDIATE DISPLAYS
|
|
if ((i_length + 4) == (min_tmp + 64))
|
|
begin
|
|
// starting length is min_tmp, ending length is (min_tmp + 64)
|
|
$display(" pads appending to packets is NOT selected");
|
|
$display(" ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
|
min_tmp, (min_tmp + 64));
|
|
// set padding, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
else if ((i_length + 4) == (max_tmp - 16))
|
|
begin
|
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
|
$display(" pads appending to packets is selected");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
|
(min_tmp + 64 + 128), tmp_data);
|
|
// reset padding, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
else if ((i_length + 4) == max_tmp)
|
|
begin
|
|
$display(" pads appending to packets is NOT selected");
|
|
$display(" ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
|
(max_tmp - (4 + 16)), max_tmp);
|
|
end
|
|
// set length (loop variable)
|
|
if ((i_length + 4) < (min_tmp + 64))
|
|
i_length = i_length + 1;
|
|
else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
|
|
begin
|
|
i_length = i_length + 128;
|
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
|
end
|
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
|
i_length = max_tmp - (4 + 16);
|
|
else if ((i_length + 4) >= (max_tmp - 16))
|
|
i_length = i_length + 1;
|
|
else
|
|
begin
|
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
|
#10 $stop;
|
|
end
|
|
end
|
|
// disable TX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packet synchronization with receive ////
|
//// Test transmit packets (DELAYED CRC) from MINFL to MAXFL ////
|
//// disable/enable ( 10Mbps ). ////
|
//// sizes at one TX buffer decriptor ( 100Mbps ). ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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if (test_num == 2) //
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if (test_num == 23) //
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begin
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begin
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// TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
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// TEST 23: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
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test_name = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
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test_name = "TEST 23: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
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`TIME; $display(" TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
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`TIME; $display(" TEST 23: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
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|
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// unmask interrupts
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max_tmp = 0;
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wait (wbm_working == 0);
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min_tmp = 0;
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wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
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// set one TX buffer descriptor - must be set before TX enable
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`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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// set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
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wait (wbm_working == 0);
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wait (wbm_working == 0);
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wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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// disable RX, set full-duplex mode, NO receive small, NO correct IFG
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// enable TX, set full-duplex mode, NO padding and CRC appending
|
wait (wbm_working == 0);
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wait (wbm_working == 0);
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wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
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wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
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`ETH_MODER_PRO | `ETH_MODER_BRO,
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4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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// prepare two packets of MAXFL length
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// prepare two packets of MAXFL length
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wait (wbm_working == 0);
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wait (wbm_working == 0);
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wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
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max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
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min_tmp = tmp[31:16];
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min_tmp = tmp[31:16];
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st_data = 8'h0F;
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st_data = 8'h5A;
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set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
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set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
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append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
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st_data = 8'h10;
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st_data = 8'h1A;
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set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
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set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
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append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
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// check WB INT signal
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// check WB INT signal
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if (wb_int !== 1'b0)
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if (wb_int !== 1'b0)
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begin
|
begin
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test_fail("WB INT signal should not be set");
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test_fail("WB INT signal should not be set");
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fail = fail + 1;
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fail = fail + 1;
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end
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end
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|
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// write to phy's control register for 10Mbps
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// write to phy's control register for 100Mbps
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#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
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#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
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#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
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#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
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speed = 10;
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speed = 100;
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frame_started = 0;
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frame_ended = 0;
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wait_for_frame = 0;
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check_frame = 0;
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stop_checking_frame = 0;
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first_fr_received = 1; // at the beginning the first frame of each two will be received!
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num_of_frames = 0; //
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i_length = (min_tmp - 4);
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num_of_bd = 0;
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while (i_length <= (max_tmp - 4))
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i_length = (min_tmp + 1); // 5 bytes longer than MINFL
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while (i_length < (max_tmp - 4))
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|
begin
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begin
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// choose generating carrier sense and collision
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// choose generating carrier sense and collision
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case (num_of_frames[1:0])
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case (i_length[1:0])
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2'h0: // Interrupt is generated
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2'h0: // Interrupt is generated
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begin
|
begin
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// enable interrupt generation
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// enable interrupt generation
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set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
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set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
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// unmask interrupts
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wait (wbm_working == 0);
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wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
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`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and no collision
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// not detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.carrier_sense_tx_fd_detect(0);
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eth_phy.collision(0);
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eth_phy.collision(0);
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end
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end
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2'h1: // Interrupt is generated
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2'h1: // Interrupt is not generated
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begin
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begin
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// enable interrupt generation
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// enable interrupt generation
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set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
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set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
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// mask interrupts
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wait (wbm_working == 0);
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wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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// detect carrier sense in FD and no collision
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// detect carrier sense in FD and no collision
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eth_phy.no_carrier_sense_rx_fd_detect(1);
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eth_phy.carrier_sense_tx_fd_detect(1);
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eth_phy.collision(0);
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eth_phy.collision(0);
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end
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end
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2'h2: // Interrupt is generated
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2'h2: // Interrupt is not generated
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begin
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begin
|
// disable interrupt generation
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// disable interrupt generation
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set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
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set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
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// unmask interrupts
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wait (wbm_working == 0);
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wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
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`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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// not detect carrier sense in FD and set collision
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// not detect carrier sense in FD and set collision
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eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.carrier_sense_tx_fd_detect(0);
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eth_phy.collision(1);
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eth_phy.collision(1);
|
end
|
end
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default: // 2'h3: // Interrupt is generated
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default: // 2'h3: // Interrupt is not generated
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begin
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begin
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// disable interrupt generation
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// disable interrupt generation
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set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
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set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
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// mask interrupts
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|
wait (wbm_working == 0);
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wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
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// detect carrier sense in FD and set collision
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// detect carrier sense in FD and set collision
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
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eth_phy.carrier_sense_tx_fd_detect(1);
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eth_phy.collision(1);
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eth_phy.collision(1);
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end
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end
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endcase
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endcase
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eth_phy.set_tx_mem_addr(max_tmp);
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// set wrap bit
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// set wrap bit
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set_rx_bd_wrap(118);
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set_tx_bd_wrap(0);
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set_rx_bd_empty(118, 118);
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set_tx_bd_ready(0, 0);
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check_frame = 0;
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#1 check_tx_bd(0, data);
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stop_checking_frame = 0;
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if (i_length < min_tmp) // just first four
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tmp_data = 0;
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fork
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begin // enable RX MAC on first of each two packets - every second should be recived normaly
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if (num_of_frames[0] == 1'b0)
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begin
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repeat(1) @(posedge wb_clk);
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if (num_of_frames[1] == 1'b0)
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begin
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repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
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end
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else
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begin
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@(posedge mrx_clk);
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repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
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end
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// enable RX, set full-duplex mode, NO receive small, NO correct IFG
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wbm_init_waits = 4'h0;
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wbm_subseq_waits = 4'h0;
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#1 wait (wbm_working == 0);
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wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
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`ETH_MODER_PRO | `ETH_MODER_BRO,
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4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
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end
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end
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begin // send a packet from PHY RX
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repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
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if (num_of_frames[1] == 1'b0)
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begin
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set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
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#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
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end
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else
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begin
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set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
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#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
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end
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end
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begin: send_packet0
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wait (MRxDV === 1'b1); // start transmit
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wait (MRxDV === 1'b0); // end transmit
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check_frame = 1;
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repeat(10) @(posedge mrx_clk);
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repeat(15) @(posedge wb_clk);
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stop_checking_frame = 1;
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end
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begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
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@(posedge eth_sl_wb_ack_o or posedge MRxDV);
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if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
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begin
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tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
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end
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else if (MRxDV === 1'b1)
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begin
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begin
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while (eth_sl_wb_ack_o === 1'b0)
|
while (data[15] === 1)
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begin
|
begin
|
|
#1 check_tx_bd(0, data);
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@(posedge wb_clk);
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@(posedge wb_clk);
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tmp_data = tmp_data + 1;
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|
end
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end
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tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
|
repeat (1) @(posedge wb_clk);
|
end
|
end
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else if (eth_sl_wb_ack_o === 1'b1)
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else if (i_length > (max_tmp - 8)) // just last four
|
begin
|
begin
|
@(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
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tmp = 0;
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while (MRxDV === 1'b0)
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wait (MTxEn === 1'b1); // start transmit
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|
while (tmp < (i_length - 20))
|
begin
|
begin
|
|
#1 tmp = tmp + 1;
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@(posedge wb_clk);
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@(posedge wb_clk);
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tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
|
|
end
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|
end
|
end
|
end
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#1 check_tx_bd(0, data);
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begin // check packet
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while (data[15] === 1)
|
wait (check_frame == 1);
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check_rx_bd(118, tmp_bd);
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|
while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
|
|
begin
|
begin
|
#1 check_rx_bd(118, tmp_bd);
|
#1 check_tx_bd(0, data);
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@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
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end
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if (num_of_frames[0] == 1'b0)
|
repeat (1) @(posedge wb_clk);
|
begin
|
|
if (tmp_bd[15] === 1)
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|
begin
|
|
if (first_fr_received == 1)
|
|
begin
|
|
first_fr_received = 0;
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|
$display(" %0d packets (without this one) are checked - packets are received by two in a set",
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num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
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|
$display(" From this moment:");
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|
$display(" first one of two packets (including this one) is not accepted due to late RX enable");
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|
if (tmp_data[31])
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|
$display(" ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
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|
else
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|
$display(" ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
|
|
end
|
end
|
// check FB, etc.
|
else
|
if (tmp_bd[31:0] !== 32'h0000_E000)
|
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status of NOT received packet is not correct: %0h", tmp_bd[31:0]);
|
wait (MTxEn === 1'b1); // start transmit
|
test_fail("RX buffer descriptor status of NOT received packet is not correct");
|
#1 check_tx_bd(0, data);
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fail = fail + 1;
|
if (data[15] !== 1)
|
end
|
|
end
|
|
// else // (tmp_bd[15] === 0) - check FB, packet, etc.
|
|
end
|
|
else // (num_of_frames[0] == 1'b1)
|
|
begin
|
begin
|
if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
begin // check NOTHING
|
|
`TIME; $display("*E RX packet should be accepted, buffer descriptor is not correct: %0h", tmp_bd[31:0]);
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|
test_fail("RX packet should be accepted, buffer descriptor is not correct");
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|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// else // (tmp_bd[15] === 0) - check FB, packet, etc.
|
wait (MTxEn === 1'b0); // end transmit
|
|
while (data[15] === 1)
|
|
begin
|
|
#1 check_tx_bd(0, data);
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|
@(posedge wb_clk);
|
end
|
end
|
if (stop_checking_frame == 0)
|
repeat (1) @(posedge wb_clk);
|
disable send_packet1;
|
|
end
|
end
|
join
|
|
// ONLY IF packet was received!
|
|
if (tmp_bd[15] === 0)
|
|
begin
|
|
// check length of a PACKET
|
// check length of a PACKET
|
if (tmp_bd[31:16] != (i_length + 4))
|
if (eth_phy.tx_len != (i_length + 4))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
test_fail("Wrong length of the packet out from MAC");
|
tmp_bd[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check received RX packet data and CRC
|
// check transmitted TX packet data
|
if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
|
if (i_length[0] == 0)
|
begin
|
|
if (num_of_frames[1] == 1'b0)
|
|
begin
|
begin
|
check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
|
check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
|
check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
|
end
|
end
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
`TIME; $display("*E Wrong data of the received packet");
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
// check transmited TX packet CRC
|
else // if PREVIOUS RX buffer descriptor was ready
|
check_tx_crc_delayed(max_tmp, i_length, 1'b0, tmp); // length without CRC
|
begin
|
if (tmp > 0)
|
if (num_of_frames[1] == 1'b0)
|
|
begin
|
begin
|
check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
test_fail("Wrong CRC of the transmitted packet");
|
|
fail = fail + 1;
|
end
|
end
|
else
|
// check WB INT signal
|
|
if (i_length[1:0] == 2'h0)
|
begin
|
begin
|
check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
if (wb_int !== 1'b1)
|
end
|
|
if (tmp > 0)
|
|
begin
|
begin
|
`TIME; $display("*E Wrong data of the received packet");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("Wrong data of the received packet");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
end
|
else
|
// check WB INT signal
|
|
if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
|
|
begin
|
begin
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else
|
// check TX buffer descriptor of a packet
|
|
check_tx_bd(0, data);
|
|
if (i_length[1] == 1'b0) // interrupt enabled
|
begin
|
begin
|
if (wb_int !== 1'b1)
|
if (data[15:0] !== 16'h7800)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("WB INT signal should be set");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check RX buffer descriptor of a packet - only 15 LSBits
|
else // interrupt not enabled
|
check_rx_bd(118, data);
|
|
if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
|
|
begin
|
begin
|
if (data[15:0] !== 16'hE000)
|
if (data[15:0] !== 16'h3800)
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else // interrupt enabled
|
|
begin
|
|
if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
|
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
|
// clear TX buffer descriptor
|
|
clear_tx_bd(0, 0);
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
begin
|
begin
|
if (data !== 0)
|
if ((data & `ETH_INT_TXB) !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
|
`TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Any of interrupts was set");
|
test_fail("Interrupt Transmit Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
if ((data & (~`ETH_INT_TXB)) !== 0)
|
else
|
|
begin
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Interrupt Receive Buffer was not set");
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
end
|
|
else
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
if (data !== 0)
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
begin
|
|
`TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h", data);
|
|
test_fail("Any of interrupts (except Transmit Buffer) was set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 11859... |
Line 11774... |
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// disable RX after two packets
|
// INTERMEDIATE DISPLAYS
|
if (num_of_frames[0] == 1'b1)
|
if ((i_length + 4) == (min_tmp + 64))
|
begin
|
begin
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// starting length is min_tmp, ending length is (min_tmp + 64)
|
|
$display(" pads appending to packets is NOT selected");
|
|
$display(" ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
|
min_tmp, (min_tmp + 64));
|
|
// set padding, remain the rest
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, 4'h0, 4'h0); // write ASAP
|
|
end
|
end
|
// the number of frame transmitted
|
else if ((i_length + 4) == (max_tmp - 16))
|
num_of_frames = num_of_frames + 1;
|
begin
|
num_of_bd = 0;
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
// set length (LOOP variable)
|
$display(" pads appending to packets is selected");
|
if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
i_length = (max_tmp - 4);
|
(min_tmp + 64 + 128), tmp_data);
|
@(posedge wb_clk);
|
// reset padding, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
// disable RX
|
else if ((i_length + 4) == max_tmp)
|
|
begin
|
|
$display(" pads appending to packets is NOT selected");
|
|
$display(" ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
|
(max_tmp - (4 + 16)), max_tmp);
|
|
end
|
|
// set length (loop variable)
|
|
if ((i_length + 4) < (min_tmp + 64))
|
|
i_length = i_length + 1;
|
|
else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
|
|
begin
|
|
i_length = i_length + 128;
|
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
|
end
|
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
|
i_length = max_tmp - (4 + 16);
|
|
else if ((i_length + 4) >= (max_tmp - 16))
|
|
i_length = i_length + 1;
|
|
else
|
|
begin
|
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
|
#10 $stop;
|
|
end
|
|
end
|
|
// disable TX
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
|
end // for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
|
|
|
|
end
|
|
endtask // test_mac_full_duplex_transmit
|
|
|
|
|
|
task test_mac_full_duplex_receive;
|
|
input [31:0] start_task;
|
|
input [31:0] end_task;
|
|
integer bit_start_1;
|
|
integer bit_end_1;
|
|
integer bit_start_2;
|
|
integer bit_end_2;
|
|
integer num_of_reg;
|
|
integer num_of_frames;
|
|
integer num_of_bd;
|
|
integer i_addr;
|
|
integer i_data;
|
|
integer i_length;
|
|
integer tmp_len;
|
|
integer tmp_bd;
|
|
integer tmp_bd_num;
|
|
integer tmp_data;
|
|
integer tmp_ipgt;
|
|
integer test_num;
|
|
reg [31:0] tx_bd_num;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
|
|
reg [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
|
|
integer i;
|
|
integer i1;
|
|
integer i2;
|
|
integer i3;
|
|
integer fail;
|
|
integer speed;
|
|
reg frame_started;
|
|
reg frame_ended;
|
|
reg wait_for_frame;
|
|
reg check_frame;
|
|
reg stop_checking_frame;
|
|
reg first_fr_received;
|
|
reg [31:0] addr;
|
|
reg [31:0] data;
|
|
reg [31:0] tmp;
|
|
reg [ 7:0] st_data;
|
|
reg [15:0] max_tmp;
|
|
reg [15:0] min_tmp;
|
|
begin
|
|
// MAC FULL DUPLEX RECEIVE TEST
|
|
test_heading("MAC FULL DUPLEX RECEIVE TEST");
|
|
$display(" ");
|
|
$display("MAC FULL DUPLEX RECEIVE TEST");
|
|
fail = 0;
|
|
|
|
// reset MAC registers
|
|
hard_reset;
|
|
// set wb slave response
|
|
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
|
|
|
|
/*
|
|
TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
|
|
-------------------------------------------------------------------------------------
|
|
set_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
|
|
set_tx_bd_wrap
|
|
(tx_bd_num_end[6:0]);
|
|
set_tx_bd_ready
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
check_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_status[31:0]);
|
|
clear_tx_bd
|
|
(tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and control RX buffer descriptors:
|
|
------------------------------------------------
|
|
set_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
|
|
set_rx_bd_wrap
|
|
(rx_bd_num_end[6:0]);
|
|
set_rx_bd_empty
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
check_rx_bd
|
|
(rx_bd_num_end[6:0], rx_bd_status);
|
|
clear_rx_bd
|
|
(rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
|
|
|
|
TASKS for set and check TX packets:
|
|
-----------------------------------
|
|
set_tx_packet
|
|
(txpnt[31:0], len[15:0], eth_start_data[7:0]);
|
|
check_tx_packet
|
|
(txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
|
|
|
|
TASKS for set and check RX packets:
|
|
-----------------------------------
|
|
set_rx_packet
|
|
(rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
|
|
check_rx_packet
|
|
(rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
|
|
|
|
TASKS for append and check CRC to/of TX packet:
|
|
-----------------------------------------------
|
|
append_tx_crc
|
|
(txpnt_wb[31:0], len[15:0], negated_crc);
|
|
check_tx_crc
|
|
(txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
|
|
|
|
TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
|
|
--------------------------------------------------------------------------------
|
|
append_rx_crc
|
|
(rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
|
|
*/
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packet synchronization with receive ////
|
//// test_mac_full_duplex_receive: ////
|
|
//// ////
|
|
//// 0: Test no receive when all buffers are TX ( 10Mbps ). ////
|
|
//// 1: Test no receive when all buffers are TX ( 100Mbps ). ////
|
|
//// 2: Test receive packet synchronization with receive ////
|
|
//// disable/enable ( 10Mbps ). ////
|
|
//// 3: Test receive packet synchronization with receive ////
|
//// disable/enable ( 100Mbps ). ////
|
//// disable/enable ( 100Mbps ). ////
|
|
//// 4: Test receive packets from MINFL to MAXFL sizes at ////
|
|
//// one RX buffer decriptor ( 10Mbps ). ////
|
|
//// 5: Test receive packets from MINFL to MAXFL sizes at ////
|
|
//// one RX buffer decriptor ( 100Mbps ). ////
|
//// ////
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
|
begin
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) //
|
//// ////
|
|
//// Test no receive when all buffers are TX ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 0) //
|
begin
|
begin
|
// TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
|
// TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
|
test_name = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
|
test_name = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
|
`TIME; $display(" TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
|
`TIME; $display(" TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
|
|
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
|
// set all buffer descriptors to TX - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare two packets of MAXFL length
|
|
wait (wbm_working == 0);
|
// write to phy's control register for 10Mbps
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
min_tmp = tmp[31:16];
|
speed = 10;
|
st_data = 8'h0F;
|
|
|
i = 0;
|
|
while (i < 128)
|
|
begin
|
|
for (i1 = 0; i1 <= i; i1 = i1 + 1)
|
|
begin
|
|
set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
|
|
append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
|
|
set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
|
|
end
|
|
set_rx_bd_wrap(i);
|
|
set_rx_bd_empty(0, i);
|
|
for (i1 = 0; i1 <= i; i1 = i1 + 1)
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
@(posedge mrx_clk);
|
|
for (i2 = 0; i2 < 20; i2 = i2 + 1)
|
|
begin
|
|
check_rx_bd(0, tmp);
|
|
#1;
|
|
if (tmp[15] === 1'b0)
|
|
begin
|
|
test_fail("Receive should not start at all");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
|
|
end
|
|
if (tmp[7:0] !== 0)
|
|
begin
|
|
test_fail("Receive should not be finished since it should not start at all");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Receive of should not be finished since it should not start at all");
|
|
end
|
|
@(posedge wb_clk);
|
|
end
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (tmp[6:0] !== 0)
|
|
begin
|
|
test_fail("Receive should not get INT since it should not start at all");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Receive of should not get INT since it should not start at all");
|
|
end
|
|
clear_rx_bd(0, i);
|
|
if ((i < 5) || (i > 124))
|
|
i = i + 1;
|
|
else
|
|
i = i + 120;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test no receive when all buffers are TX ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 1) //
|
|
begin
|
|
// TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
|
|
test_name = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
|
|
`TIME; $display(" TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
|
|
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set all buffer descriptors to TX - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 100Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 100;
|
|
|
|
i = 0;
|
|
while (i < 128)
|
|
begin
|
|
for (i1 = 0; i1 <= i; i1 = i1 + 1)
|
|
begin
|
|
set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
|
|
append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
|
|
set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
|
|
end
|
|
set_rx_bd_wrap(i);
|
|
set_rx_bd_empty(0, i);
|
|
for (i1 = 0; i1 <= i; i1 = i1 + 1)
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
@(posedge mrx_clk);
|
|
for (i2 = 0; i2 < 20; i2 = i2 + 1)
|
|
begin
|
|
check_rx_bd(0, tmp);
|
|
#1;
|
|
if (tmp[15] === 1'b0)
|
|
begin
|
|
test_fail("Receive should not start at all");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
|
|
end
|
|
if (tmp[7:0] !== 0)
|
|
begin
|
|
test_fail("Receive should not be finished since it should not start at all");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Receive of should not be finished since it should not start at all");
|
|
end
|
|
@(posedge wb_clk);
|
|
end
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (tmp[6:0] !== 0)
|
|
begin
|
|
test_fail("Receive should not get INT since it should not start at all");
|
|
fail = fail + 1;
|
|
`TIME; $display("*E Receive of should not get INT since it should not start at all");
|
|
end
|
|
clear_rx_bd(0, i);
|
|
if ((i < 5) || (i > 124))
|
|
i = i + 1;
|
|
else
|
|
i = i + 120;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packet synchronization with receive ////
|
|
//// disable/enable ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 2) //
|
|
begin
|
|
// TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
|
|
test_name = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
|
|
`TIME; $display(" TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
|
|
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// prepare two packets of MAXFL length
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
|
min_tmp = tmp[31:16];
|
|
st_data = 8'h0F;
|
set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
|
append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
|
st_data = 8'h1A;
|
st_data = 8'h1A;
|
set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
|
append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
|
| Line 11930... |
Line 12186... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 10;
|
|
|
frame_started = 0;
|
frame_started = 0;
|
frame_ended = 0;
|
frame_ended = 0;
|
wait_for_frame = 0;
|
wait_for_frame = 0;
|
check_frame = 0;
|
check_frame = 0;
|
| Line 12024... |
Line 12280... |
begin
|
begin
|
set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
|
set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
end
|
end
|
end
|
end
|
begin: send_packet1
|
begin: send_packet0
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b0); // end transmit
|
wait (MRxDV === 1'b0); // end transmit
|
check_frame = 1;
|
check_frame = 1;
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
repeat(15) @(posedge wb_clk);
|
repeat(15) @(posedge wb_clk);
|
| Line 12258... |
Line 12514... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets form MINFL to MAXFL sizes at ////
|
//// Test receive packet synchronization with receive ////
|
//// one RX buffer decriptor ( 10Mbps ). ////
|
//// disable/enable ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 4) //
|
if (test_num == 3) //
|
begin
|
begin
|
// TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
|
// TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
|
test_name = "TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )";
|
test_name = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
|
`TIME; $display(" TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )");
|
`TIME; $display(" TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
|
|
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
// set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO,// | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare two packets of MAXFL length
|
// prepare two packets of MAXFL length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
st_data = 8'h0F;
|
st_data = 8'h0F;
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
|
st_data = 8'h1A;
|
st_data = 8'h1A;
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
|
append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 100;
|
|
|
i_length = (min_tmp - 4);
|
frame_started = 0;
|
while (i_length <= (max_tmp - 4))
|
frame_ended = 0;
|
|
wait_for_frame = 0;
|
|
check_frame = 0;
|
|
stop_checking_frame = 0;
|
|
first_fr_received = 1; // at the beginning the first frame of each two will be received!
|
|
|
|
num_of_frames = 0; //
|
|
num_of_bd = 0;
|
|
i_length = (min_tmp + 1); // 5 bytes longer than MINFL
|
|
while (i_length < (max_tmp - 4))
|
begin
|
begin
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
// choose generating carrier sense and collision
|
case (i_length[1:0])
|
case (num_of_frames[1:0])
|
2'h0: // Interrupt is generated
|
2'h0: // Interrupt is generated
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
end
|
end
|
2'h1: // Interrupt is not generated
|
2'h1: // Interrupt is generated
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
|
// mask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// detect carrier sense in FD and no collision
|
// detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
end
|
end
|
2'h2: // Interrupt is not generated
|
2'h2: // Interrupt is generated
|
begin
|
begin
|
// disable interrupt generation
|
// disable interrupt generation
|
set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
|
set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// not detect carrier sense in FD and set collision
|
// not detect carrier sense in FD and set collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(1);
|
eth_phy.collision(1);
|
end
|
end
|
default: // 2'h3: // Interrupt is not generated
|
default: // 2'h3: // Interrupt is generated
|
begin
|
begin
|
// disable interrupt generation
|
// disable interrupt generation
|
set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
|
// mask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// detect carrier sense in FD and set collision
|
// detect carrier sense in FD and set collision
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.collision(1);
|
eth_phy.collision(1);
|
end
|
end
|
endcase
|
endcase
|
if (i_length[0] == 1'b0)
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
else
|
|
append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
|
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(127);
|
set_rx_bd_wrap(118);
|
set_rx_bd_empty(127, 127);
|
set_rx_bd_empty(118, 118);
|
|
check_frame = 0;
|
|
stop_checking_frame = 0;
|
|
tmp_data = 0;
|
fork
|
fork
|
|
begin // enable RX MAC on first of each two packets - every second should be recived normaly
|
|
if (num_of_frames[0] == 1'b0)
|
begin
|
begin
|
if (i_length[0] == 1'b0)
|
repeat(1) @(posedge wb_clk);
|
|
if (num_of_frames[1] == 1'b0)
|
|
begin
|
|
repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
|
|
end
|
|
else
|
|
begin
|
|
@(posedge mrx_clk);
|
|
repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
|
|
end
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wbm_init_waits = 4'h0;
|
|
wbm_subseq_waits = 4'h0;
|
|
#1 wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
|
|
end
|
|
end
|
|
begin // send a packet from PHY RX
|
|
repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
|
|
if (num_of_frames[1] == 1'b0)
|
|
begin
|
|
set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
end
|
else
|
else
|
|
begin
|
|
set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
|
end
|
|
end
|
|
begin: send_packet1
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
check_frame = 1;
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(15) @(posedge wb_clk);
|
|
stop_checking_frame = 1;
|
end
|
end
|
|
begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
|
|
@(posedge eth_sl_wb_ack_o or posedge MRxDV);
|
|
if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
|
begin
|
begin
|
#1 check_rx_bd(127, data);
|
tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
|
if (i_length < min_tmp) // just first four
|
end
|
|
else if (MRxDV === 1'b1)
|
begin
|
begin
|
while (data[15] === 1)
|
while (eth_sl_wb_ack_o === 1'b0)
|
begin
|
begin
|
#1 check_rx_bd(127, data);
|
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
|
tmp_data = tmp_data + 1;
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
|
end
|
end
|
else
|
else if (eth_sl_wb_ack_o === 1'b1)
|
begin
|
begin
|
wait (MRxDV === 1'b1); // start transmit
|
@(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
|
#1 check_rx_bd(127, data);
|
while (MRxDV === 1'b0)
|
if (data[15] !== 1)
|
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
@(posedge wb_clk);
|
fail = fail + 1;
|
tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
|
end
|
end
|
wait (MRxDV === 1'b0); // end transmit
|
end
|
while (data[15] === 1)
|
end
|
|
begin // check packet
|
|
wait (check_frame == 1);
|
|
check_rx_bd(118, tmp_bd);
|
|
while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
|
begin
|
begin
|
#1 check_rx_bd(127, data);
|
#1 check_rx_bd(118, tmp_bd);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
if (num_of_frames[0] == 1'b0)
|
|
begin
|
|
if (tmp_bd[15] === 1)
|
|
begin
|
|
if (first_fr_received == 1)
|
|
begin
|
|
first_fr_received = 0;
|
|
$display(" %0d packets (without this one) are checked - packets are received by two in a set",
|
|
num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
|
|
$display(" From this moment:");
|
|
$display(" first one of two packets (including this one) is not accepted due to late RX enable");
|
|
if (tmp_data[31])
|
|
$display(" ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
|
|
else
|
|
$display(" ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
|
|
end
|
|
// check FB, etc.
|
|
if (tmp_bd[31:0] !== 32'h0000_E000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status of NOT received packet is not correct: %0h", tmp_bd[31:0]);
|
|
test_fail("RX buffer descriptor status of NOT received packet is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// else // (tmp_bd[15] === 0) - check FB, packet, etc.
|
|
end
|
|
else // (num_of_frames[0] == 1'b1)
|
|
begin
|
|
if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
|
|
begin // check NOTHING
|
|
`TIME; $display("*E RX packet should be accepted, buffer descriptor is not correct: %0h", tmp_bd[31:0]);
|
|
test_fail("RX packet should be accepted, buffer descriptor is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// else // (tmp_bd[15] === 0) - check FB, packet, etc.
|
end
|
end
|
|
if (stop_checking_frame == 0)
|
|
disable send_packet1;
|
end
|
end
|
join
|
join
|
|
// ONLY IF packet was received!
|
|
if (tmp_bd[15] === 0)
|
|
begin
|
// check length of a PACKET
|
// check length of a PACKET
|
if (data[31:16] != (i_length + 4))
|
if (tmp_bd[31:16] != (i_length + 4))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
data[31:16], (i_length + 4));
|
tmp_bd[31:16], (i_length + 4));
|
test_fail("Wrong length of the packet out from PHY");
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// checking in the following if statement is performed only for first and last 64 lengths
|
|
// check received RX packet data and CRC
|
// check received RX packet data and CRC
|
if (i_length[0] == 1'b0)
|
if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
|
begin
|
begin
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
if (num_of_frames[1] == 1'b0)
|
|
begin
|
|
check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
|
check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
|
end
|
end
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
`TIME; $display("*E Wrong data of the received packet");
|
`TIME; $display("*E Wrong data of the received packet");
|
test_fail("Wrong data of the received packet");
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check WB INT signal
|
end
|
if (i_length[1:0] == 2'h0)
|
else // if PREVIOUS RX buffer descriptor was ready
|
begin
|
begin
|
if (wb_int !== 1'b1)
|
if (num_of_frames[1] == 1'b0)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
test_fail("WB INT signal should be set");
|
end
|
|
else
|
|
begin
|
|
check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
|
end
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else
|
end
|
|
// check WB INT signal
|
|
if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
|
begin
|
begin
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check RX buffer descriptor of a packet
|
else
|
check_rx_bd(127, data);
|
|
if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
|
|
begin
|
begin
|
if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
|
if (wb_int !== 1'b1)
|
((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// check RX buffer descriptor of a packet - only 15 LSBits
|
|
check_rx_bd(118, data);
|
|
if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
|
|
begin
|
|
if (data[15:0] !== 16'hE000)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else // interrupt not enabled
|
else // interrupt enabled
|
begin
|
begin
|
if ( ((data[15:0] !== 16'h2080) && (i_length[0] == 1'b0)) ||
|
if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
|
((data[15:0] !== 16'h2080) && (i_length[0] == 1'b1)) )
|
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// clear RX buffer descriptor for first 4 frames
|
|
if (i_length < min_tmp)
|
|
clear_rx_bd(127, 127);
|
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
|
|
begin
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
|
|
test_fail("Any of interrupts was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
begin
|
begin
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Receive Buffer was not set");
|
test_fail("Interrupt Receive Buffer was not set");
|
| Line 12484... |
Line 12842... |
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else
|
|
begin
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// disable RX after two packets
|
if ((i_length + 4) == (min_tmp + 64))
|
if (num_of_frames[0] == 1'b1)
|
begin
|
begin
|
// starting length is min_tmp, ending length is (min_tmp + 64)
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
$display(" receive small packets is NOT selected");
|
|
$display(" ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
|
min_tmp, (min_tmp + 64));
|
|
// set receive small, remain the rest
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, 4'h0, 4'h0); // write ASAP
|
end
|
end
|
else if ((i_length + 4) == (max_tmp - 16))
|
// the number of frame transmitted
|
begin
|
num_of_frames = num_of_frames + 1;
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
num_of_bd = 0;
|
$display(" receive small packets is selected");
|
// set length (LOOP variable)
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
|
(min_tmp + 64 + 128), tmp_data);
|
i_length = (max_tmp - 4);
|
// reset receive small, remain the rest
|
@(posedge wb_clk);
|
|
end
|
|
// disable RX
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
else if ((i_length + 4) == max_tmp)
|
|
begin
|
|
$display(" receive small packets is NOT selected");
|
|
$display(" ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
|
(max_tmp - (4 + 16)), max_tmp);
|
|
end
|
|
// set length (loop variable)
|
|
if ((i_length + 4) < (min_tmp + 64))
|
|
i_length = i_length + 1;
|
|
else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
|
|
begin
|
|
i_length = i_length + 128;
|
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
|
end
|
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
|
i_length = max_tmp - (4 + 16);
|
|
else if ((i_length + 4) >= (max_tmp - 16))
|
|
i_length = i_length + 1;
|
|
else
|
|
begin
|
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
|
#10 $stop;
|
|
end
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
| Line 12565... |
Line 12882... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets form MINFL to MAXFL sizes at ////
|
//// Test receive packets from MINFL to MAXFL sizes at ////
|
//// one RX buffer decriptor ( 100Mbps ). ////
|
//// one RX buffer decriptor ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 5) //
|
if (test_num == 4) //
|
begin
|
begin
|
// TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
|
// TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
|
test_name = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
|
test_name = "TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )";
|
`TIME; $display(" TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
|
`TIME; $display(" TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )");
|
|
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 12585... |
Line 12902... |
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO,// | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare two packets of MAXFL length
|
// prepare two packets of MAXFL length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
st_data = 8'h0F;
|
st_data = 8'h0F;
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
st_data = 8'h1A;
|
st_data = 8'h1A;
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 10;
|
|
|
i_length = (min_tmp - 4);
|
i_length = (min_tmp - 4);
|
while (i_length <= (max_tmp - 4))
|
while (i_length <= (max_tmp - 4))
|
begin
|
begin
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
| Line 12750... |
Line 13067... |
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
check_rx_bd(127, data);
|
check_rx_bd(127, data);
|
if (i_length[1] == 1'b0) // interrupt enabled
|
if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
|
begin
|
begin
|
if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
|
if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
|
((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
|
((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
| Line 12872... |
Line 13189... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets form MINFL to MAXFL sizes at ////
|
//// Test receive packets from MINFL to MAXFL sizes at ////
|
//// maximum RX buffer decriptors ( 10Mbps ). ////
|
//// one RX buffer decriptor ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 6) //
|
if (test_num == 5) //
|
begin
|
begin
|
// TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
|
// TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
|
test_name = "TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )";
|
test_name = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
|
`TIME; $display(" TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )");
|
`TIME; $display(" TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
|
// set maximum RX buffer descriptors (128) - must be set before RX enable
|
|
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare two packets of MAXFL length
|
// prepare two packets of MAXFL length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
st_data = 8'hAC;
|
st_data = 8'h0F;
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
st_data = 8'h35;
|
st_data = 8'h1A;
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
num_of_frames = 0;
|
|
num_of_bd = 0;
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 100;
|
|
|
i_length = (min_tmp - 4);
|
i_length = (min_tmp - 4);
|
while (i_length <= (max_tmp - 4))
|
while (i_length <= (max_tmp - 4))
|
begin
|
begin
|
// append CRC to packet
|
// choose generating carrier sense and collision for first and last 64 lengths of frames
|
if (i_length[0] == 1'b0)
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
else
|
|
append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
|
|
// choose generating carrier sense and collision
|
|
case (i_length[1:0])
|
case (i_length[1:0])
|
2'h0: // Interrupt is generated
|
2'h0: // Interrupt is generated
|
begin
|
begin
|
// Reset_tx_bd nable interrupt generation
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
end
|
end
|
2'h1: // Interrupt is not generated
|
2'h1: // Interrupt is not generated
|
begin
|
begin
|
// set_tx_bd enable interrupt generation
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
// mask interrupts
|
// mask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// detect carrier sense in FD and no collision
|
// detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
end
|
end
|
2'h2: // Interrupt is not generated
|
2'h2: // Interrupt is not generated
|
begin
|
begin
|
// set_tx_bd disable the interrupt generation
|
// disable interrupt generation
|
|
set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
|
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and set collision
|
// not detect carrier sense in FD and set collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(1);
|
eth_phy.collision(1);
|
end
|
end
|
default: // 2'h3: // Interrupt is not generated
|
default: // 2'h3: // Interrupt is not generated
|
begin
|
begin
|
// set_tx_bd disable the interrupt generation
|
// disable interrupt generation
|
|
set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
// mask interrupts
|
// mask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// detect carrier sense in FD and set collision
|
// detect carrier sense in FD and set collision
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.collision(1);
|
eth_phy.collision(1);
|
end
|
end
|
endcase
|
endcase
|
// first 8 frames are received with RX BD 0 (wrap bit on RX BD 0)
|
if (i_length[0] == 1'b0)
|
// number of all frames is 154 (146 without first 8)
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
if (num_of_frames < 8)
|
|
begin
|
|
case (i_length[1:0])
|
|
2'h0: // Interrupt is generated
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(0, 0, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
|
// interrupts are unmasked
|
|
end
|
|
2'h1: // Interrupt is not generated
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(0, 0, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
|
// interrupts are masked
|
|
end
|
|
2'h2: // Interrupt is not generated
|
|
begin
|
|
// disable interrupt generation
|
|
set_rx_bd(0, 0, 1'b0, (`MEMORY_BASE + i_length[1:0]));
|
|
// interrupts are unmasked
|
|
end
|
|
default: // 2'h3: // Interrupt is not generated
|
|
begin
|
|
// disable interrupt generation
|
|
set_rx_bd(0, 0, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
|
// interrupts are masked
|
|
end
|
|
endcase
|
|
// set wrap bit
|
|
set_rx_bd_wrap(0);
|
|
end
|
|
// after first 8 number of frames, 128 frames form RX BD 0 to 127 will be received
|
|
else if ((num_of_frames - 8) == 0)
|
|
begin
|
|
tmp_len = i_length; // length of frame
|
|
tmp_bd_num = 0; // RX BD number
|
|
while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
|
begin
|
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
|
if (tmp_len[0] == 0)
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
else
|
set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
if ((tmp_len + 4) < (min_tmp + 128))
|
|
tmp_len = tmp_len + 1;
|
|
else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
|
|
tmp_len = 256;
|
|
else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
|
|
tmp_len = tmp_len + 128;
|
|
else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
|
|
tmp_len = max_tmp - (4 + 16);
|
|
else if ((tmp_len + 4) >= (max_tmp - 16))
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
|
end
|
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(127);
|
set_rx_bd_wrap(127);
|
end
|
set_rx_bd_empty(127, 127);
|
// after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
|
|
else if ((num_of_frames - 8) == 128)
|
|
begin
|
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
|
tmp_bd_num = 0; // TX BD number
|
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
|
begin
|
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
|
if (tmp_len[0] == 0)
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
if ((tmp_len + 4) < (min_tmp + 128))
|
|
tmp_len = tmp_len + 1;
|
|
else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
|
|
tmp_len = 256;
|
|
else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
|
|
tmp_len = tmp_len + 128;
|
|
else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
|
|
tmp_len = max_tmp - (4 + 16);
|
|
else if ((tmp_len + 4) >= (max_tmp - 16))
|
|
tmp_len = tmp_len + 1;
|
|
// set TX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
|
end
|
|
end
|
|
// set empty bit
|
|
if (num_of_frames < 8)
|
|
set_rx_bd_empty(0, 0);
|
|
else if ((num_of_frames - 8) < 128)
|
|
set_rx_bd_empty((num_of_frames - 8), (num_of_frames - 8));
|
|
else if ((num_of_frames - 136) < 19)
|
|
set_rx_bd_empty((num_of_frames - 136), (num_of_frames - 136));
|
|
// CHECK END OF RECEIVE
|
|
fork
|
fork
|
begin
|
begin
|
if (i_length[0] == 1'b0)
|
if (i_length[0] == 1'b0)
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
else
|
else
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
end
|
end
|
begin
|
begin
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(127, data);
|
if (i_length < min_tmp) // just first four
|
if (i_length < min_tmp) // just first four
|
begin
|
begin
|
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(127, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(127, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MRxDV === 1'b0); // end transmit
|
wait (MRxDV === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(127, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
end
|
end
|
| Line 13146... |
Line 13373... |
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
check_rx_bd(num_of_bd, data);
|
check_rx_bd(127, data);
|
if (i_length[1] == 1'b0) // interrupt enabled
|
if (i_length[1] == 1'b0) // interrupt enabled
|
begin
|
begin
|
if ( ((data[15:0] !== 16'h6080) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
|
if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
|
((data[15:0] !== 16'h4080) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
|
((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else // interrupt not enabled
|
else // interrupt not enabled
|
begin
|
begin
|
if ( ((data[15:0] !== 16'h2080) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
|
if ( ((data[15:0] !== 16'h2080) && (i_length[0] == 1'b0)) ||
|
((data[15:0] !== 16'h0080) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
|
((data[15:0] !== 16'h2080) && (i_length[0] == 1'b1)) )
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// clear first half of 8 frames from RX buffer descriptor 0
|
// clear RX buffer descriptor for first 4 frames
|
if (num_of_frames < 4)
|
if (i_length < min_tmp)
|
clear_rx_bd(num_of_bd, num_of_bd);
|
|
// clear BD with wrap bit
|
|
if (num_of_frames == 140)
|
|
clear_rx_bd(127, 127);
|
clear_rx_bd(127, 127);
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
| Line 13210... |
Line 13434... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if ((i_length + 4) == (min_tmp + 7))
|
if ((i_length + 4) == (min_tmp + 64))
|
begin
|
begin
|
// starting length is min_tmp, ending length is (min_tmp + 128)
|
// starting length is min_tmp, ending length is (min_tmp + 64)
|
$display(" receive small packets is NOT selected");
|
$display(" receive small packets is NOT selected");
|
$display(" using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)");
|
|
$display(" ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
$display(" ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
min_tmp, (min_tmp + 7));
|
min_tmp, (min_tmp + 64));
|
$display(" ->all packets were received on RX BD 0");
|
|
// reset receive small, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
end
|
|
else if ((i_length + 4) == (min_tmp + 128))
|
|
begin
|
|
// starting length is min_tmp, ending length is (min_tmp + 128)
|
|
$display(" receive small packets is NOT selected");
|
|
$display(" using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
(min_tmp + 8), (min_tmp + 128));
|
|
$display(" ->packets were received on RX BD %0d to RX BD %0d respectively",
|
|
1'b0, num_of_bd);
|
|
tmp_bd = num_of_bd + 1;
|
|
// set receive small, remain the rest
|
// set receive small, remain the rest
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if ((i_length + 4) == (max_tmp - 16))
|
else if ((i_length + 4) == (max_tmp - 16))
|
begin
|
begin
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
$display(" receive small packets is selected");
|
$display(" receive small packets is selected");
|
$display(" using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
(min_tmp + 64 + 128), tmp_data);
|
(min_tmp + 64 + 128), tmp_data);
|
if (tmp_bd > num_of_bd)
|
|
$display(" ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
|
|
tmp_bd, num_of_bd);
|
|
else
|
|
$display(" ->packets were received from RX BD %0d to RX BD %0d respectively",
|
|
tmp_bd, num_of_bd);
|
|
tmp_bd = num_of_bd + 1;
|
|
// reset receive small, remain the rest
|
// reset receive small, remain the rest
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if ((i_length + 4) == max_tmp)
|
else if ((i_length + 4) == max_tmp)
|
begin
|
begin
|
$display(" receive small packets is NOT selected");
|
$display(" receive small packets is NOT selected");
|
$display(" using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
$display(" ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
(max_tmp - (4 + 16)), max_tmp);
|
(max_tmp - (4 + 16)), max_tmp);
|
if (tmp_bd > num_of_bd)
|
|
$display(" ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
|
|
tmp_bd, num_of_bd);
|
|
else
|
|
$display(" ->packets were received from RX BD %0d to RX BD %0d respectively",
|
|
tmp_bd, num_of_bd);
|
|
end
|
end
|
// set length (loop variable)
|
// set length (loop variable)
|
if ((i_length + 4) < (min_tmp + 128))
|
if ((i_length + 4) < (min_tmp + 64))
|
i_length = i_length + 1;
|
i_length = i_length + 1;
|
else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
|
else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
|
i_length = 256;
|
|
else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
|
|
begin
|
begin
|
i_length = i_length + 128;
|
i_length = i_length + 128;
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
end
|
end
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
| Line 13292... |
Line 13481... |
else
|
else
|
begin
|
begin
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
#10 $stop;
|
#10 $stop;
|
end
|
end
|
// the number of frame transmitted
|
|
num_of_frames = num_of_frames + 1;
|
|
if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
|
|
num_of_bd = 0;
|
|
else
|
|
num_of_bd = num_of_bd + 1;
|
|
end
|
end
|
// disable RX
|
// disable RX
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
@(posedge wb_clk);
|
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets form MINFL to MAXFL sizes at ////
|
//// Test receive packets from MINFL to MAXFL sizes at ////
|
//// maximum RX buffer decriptors ( 100Mbps ). ////
|
//// maximum RX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 7) //
|
if (test_num == 6) //
|
begin
|
begin
|
// TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
|
// TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
|
test_name = "TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )";
|
test_name = "TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )";
|
`TIME; $display(" TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )");
|
`TIME; $display(" TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )");
|
// set maximum RX buffer descriptors (128) - must be set before RX enable
|
// set maximum RX buffer descriptors (128) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 13349... |
Line 13531... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 10;
|
|
|
i_length = (min_tmp - 4);
|
i_length = (min_tmp - 4);
|
while (i_length <= (max_tmp - 4))
|
while (i_length <= (max_tmp - 4))
|
begin
|
begin
|
// append CRC to packet
|
// append CRC to packet
|
| Line 13440... |
Line 13622... |
end
|
end
|
endcase
|
endcase
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(0);
|
set_rx_bd_wrap(0);
|
end
|
end
|
// after first 8 number of frames, 128 frames form RX BD 0 to 127 will be received
|
// after first 8 number of frames, 128 frames from RX BD 0 to 127 will be received
|
else if ((num_of_frames - 8) == 0)
|
else if ((num_of_frames - 8) == 0)
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 0; // RX BD number
|
tmp_bd_num = 0; // RX BD number
|
while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
| Line 13470... |
Line 13652... |
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(127);
|
set_rx_bd_wrap(127);
|
end
|
end
|
// after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
|
// after 128 + first 8 number of frames, 19 frames from RX BD 0 to 18 will be received
|
else if ((num_of_frames - 8) == 128)
|
else if ((num_of_frames - 8) == 128)
|
begin
|
begin
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_bd_num = 0; // TX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
| Line 13552... |
Line 13734... |
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
data[31:16], (i_length + 4));
|
data[31:16], (i_length + 4));
|
test_fail("Wrong length of the packet out from PHY");
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// checking in the following if statement is performed only for first and last 64 lengths
|
// check received RX packet data and CRC
|
// check received RX packet data and CRC
|
if (i_length[0] == 1'b0)
|
if (i_length[0] == 1'b0)
|
begin
|
begin
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
end
|
end
|
| Line 13755... |
Line 13938... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets form 0 to (MINFL + 12) sizes at ////
|
//// Test receive packets from MINFL to MAXFL sizes at ////
|
//// 8 RX buffer decriptors ( 10Mbps ). ////
|
//// maximum RX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 8) //
|
if (test_num == 7) //
|
begin
|
begin
|
// TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )
|
// TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
|
test_name = "TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )";
|
test_name = "TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )";
|
`TIME; $display(" TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )");
|
`TIME; $display(" TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )");
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
// set maximum RX buffer descriptors (128) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare two packets of MAXFL length
|
// prepare two packets of MAXFL length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 13781... |
Line 13964... |
min_tmp = tmp[31:16];
|
min_tmp = tmp[31:16];
|
st_data = 8'hAC;
|
st_data = 8'hAC;
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
st_data = 8'h35;
|
st_data = 8'h35;
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
|
num_of_frames = 0;
|
|
num_of_bd = 0;
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 100;
|
|
|
frame_ended = 0;
|
i_length = (min_tmp - 4);
|
num_of_frames = 0;// 0; // 10;
|
while (i_length <= (max_tmp - 4))
|
num_of_bd = 120;
|
|
i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
|
|
while ((i_length + 4) < 78) // (min_tmp - 4))
|
|
begin
|
begin
|
// append CRC to packet
|
// append CRC to packet
|
if ((i_length[0] == 1'b0) && (num_of_frames > 4))
|
if (i_length[0] == 1'b0)
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
else if (num_of_frames > 4)
|
else
|
append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
|
append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
|
// choose generating carrier sense and collision
|
// choose generating carrier sense and collision
|
case (i_length[1:0])
|
case (i_length[1:0])
|
2'h0:
|
2'h0: // Interrupt is generated
|
begin
|
begin
|
|
// Reset_tx_bd nable interrupt generation
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
end
|
end
|
2'h1:
|
2'h1: // Interrupt is not generated
|
begin
|
begin
|
|
// set_tx_bd enable interrupt generation
|
|
// mask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// detect carrier sense in FD and no collision
|
// detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
end
|
end
|
2'h2:
|
2'h2: // Interrupt is not generated
|
begin
|
begin
|
|
// set_tx_bd disable the interrupt generation
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// not detect carrier sense in FD and set collision
|
// not detect carrier sense in FD and set collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(1);
|
eth_phy.collision(1);
|
end
|
end
|
default: // 2'h3:
|
default: // 2'h3: // Interrupt is not generated
|
begin
|
begin
|
|
// set_tx_bd disable the interrupt generation
|
|
// mask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// detect carrier sense in FD and set collision
|
// detect carrier sense in FD and set collision
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
eth_phy.collision(1);
|
eth_phy.collision(1);
|
end
|
end
|
endcase
|
endcase
|
#1;
|
// first 8 frames are received with RX BD 0 (wrap bit on RX BD 0)
|
// first 10 frames are received with RX BD 120 (wrap bit on RX BD 120)
|
// number of all frames is 154 (146 without first 8)
|
if (num_of_frames <= 9)
|
if (num_of_frames < 8)
|
begin
|
begin
|
case (i_length[1:0])
|
case (i_length[1:0])
|
2'h0: // Interrupt is generated
|
2'h0: // Interrupt is generated
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
set_rx_bd(0, 0, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
|
// interrupts are unmasked
|
end
|
end
|
2'h1: // Interrupt is generated
|
2'h1: // Interrupt is not generated
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
set_rx_bd(0, 0, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
|
// interrupts are masked
|
end
|
end
|
2'h2: // Interrupt is generated
|
2'h2: // Interrupt is not generated
|
begin
|
begin
|
// enable interrupt generation
|
// disable interrupt generation
|
set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
set_rx_bd(0, 0, 1'b0, (`MEMORY_BASE + i_length[1:0]));
|
|
// interrupts are unmasked
|
end
|
end
|
default: // 2'h3: // Interrupt is generated
|
default: // 2'h3: // Interrupt is not generated
|
begin
|
begin
|
// enable interrupt generation
|
// disable interrupt generation
|
set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
set_rx_bd(0, 0, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
|
// interrupts are masked
|
end
|
end
|
endcase
|
endcase
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(120);
|
set_rx_bd_wrap(0);
|
end
|
end
|
// 10 <= num_of_frames < 18 => wrap set to TX BD 123
|
// after first 8 number of frames, 128 frames from RX BD 0 to 127 will be received
|
else if ((num_of_frames == 10) || (num_of_frames == 14))
|
else if ((num_of_frames - 8) == 0)
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = i_length; // length of frame
|
tmp_bd_num = 120; // RX BD number
|
tmp_bd_num = 0; // RX BD number
|
while (tmp_bd_num < 124) //
|
while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
begin
|
begin
|
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
|
else
|
else
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
if ((tmp_len + 4) < (min_tmp + 128))
|
|
tmp_len = tmp_len + 1;
|
|
else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
|
|
tmp_len = 256;
|
|
else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
|
|
tmp_len = tmp_len + 128;
|
|
else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
|
|
tmp_len = max_tmp - (4 + 16);
|
|
else if ((tmp_len + 4) >= (max_tmp - 16))
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set RX BD number
|
// set RX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(123);
|
set_rx_bd_wrap(127);
|
end
|
end
|
// 18 <= num_of_frames < 28 => wrap set to RX BD 124
|
// after 128 + first 8 number of frames, 19 frames from RX BD 0 to 18 will be received
|
else if ((num_of_frames == 18) || (num_of_frames == 23))
|
else if ((num_of_frames - 8) == 128)
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
tmp_len = tmp_len; // length of frame remaines from previous settings
|
tmp_bd_num = 120; // RX BD number
|
tmp_bd_num = 0; // TX BD number
|
while (tmp_bd_num < 125) //
|
while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
|
begin
|
begin
|
|
// if i_length[1] == 0 then enable interrupt generation otherwise disable it
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (tmp_len[0] == 0)
|
if (tmp_len[0] == 0)
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
|
else
|
else
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
if ((tmp_len + 4) < (min_tmp + 128))
|
tmp_len = tmp_len + 1;
|
tmp_len = tmp_len + 1;
|
// set RX BD number
|
else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
|
|
tmp_len = 256;
|
|
else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
|
|
tmp_len = tmp_len + 128;
|
|
else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
|
|
tmp_len = max_tmp - (4 + 16);
|
|
else if ((tmp_len + 4) >= (max_tmp - 16))
|
|
tmp_len = tmp_len + 1;
|
|
// set TX BD number
|
tmp_bd_num = tmp_bd_num + 1;
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// set wrap bit
|
|
set_rx_bd_wrap(124);
|
|
end
|
end
|
// 28 <= num_of_frames < 40 => wrap set to RX BD 125
|
// set empty bit
|
else if ((num_of_frames == 28) || (num_of_frames == 34))
|
if (num_of_frames < 8)
|
begin
|
set_rx_bd_empty(0, 0);
|
tmp_len = i_length; // length of frame
|
else if ((num_of_frames - 8) < 128)
|
tmp_bd_num = 120; // RX BD number
|
set_rx_bd_empty((num_of_frames - 8), (num_of_frames - 8));
|
while (tmp_bd_num < 126) //
|
else if ((num_of_frames - 136) < 19)
|
|
set_rx_bd_empty((num_of_frames - 136), (num_of_frames - 136));
|
|
// CHECK END OF RECEIVE
|
|
fork
|
begin
|
begin
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
if (i_length[0] == 1'b0)
|
if (tmp_len[0] == 0)
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
else
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
repeat(10) @(posedge mrx_clk);
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
|
end
|
|
// set wrap bit
|
|
set_rx_bd_wrap(125);
|
|
end
|
end
|
// 40 <= num_of_frames < 54 => wrap set to RX BD 126
|
|
else if ((num_of_frames == 40) || (num_of_frames == 47))
|
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
#1 check_rx_bd(num_of_bd, data);
|
tmp_bd_num = 120; // RX BD number
|
if (i_length < min_tmp) // just first four
|
while (tmp_bd_num < 127) //
|
|
begin
|
begin
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
while (data[15] === 1)
|
if (tmp_len[0] == 0)
|
begin
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
#1 check_rx_bd(num_of_bd, data);
|
else
|
@(posedge wb_clk);
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
|
end
|
end
|
// set wrap bit
|
repeat (1) @(posedge wb_clk);
|
set_rx_bd_wrap(126);
|
|
end
|
end
|
// 54 <= num_of_frames < 70 => wrap set to RX BD 127
|
else
|
else if ((num_of_frames == 54) || (num_of_frames == 62))
|
|
begin
|
begin
|
tmp_len = i_length; // length of frame
|
wait (MRxDV === 1'b1); // start transmit
|
tmp_bd_num = 120; // RX BD number
|
#1 check_rx_bd(num_of_bd, data);
|
while (tmp_bd_num < 128) //
|
if (data[15] !== 1)
|
begin
|
begin
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
if (tmp_len[0] == 0)
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
|
end
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
end
|
|
// 70 <= num_of_frames < 78 => wrap set to RX BD 127
|
|
else if (num_of_frames == 70)
|
|
begin
|
|
tmp_len = i_length; // length of frame
|
|
tmp_bd_num = 120; // RX BD number
|
|
while (tmp_bd_num < 128) //
|
|
begin
|
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
|
if (tmp_len[0] == 0)
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
|
end
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
end
|
|
#1;
|
|
// SET empty bit
|
|
if (num_of_frames < 10)
|
|
set_rx_bd_empty(120, 120);
|
|
else if (num_of_frames < 14)
|
|
set_rx_bd_empty((120 + num_of_frames - 10), (120 + num_of_frames - 10));
|
|
else if (num_of_frames < 18)
|
|
set_rx_bd_empty((120 + num_of_frames - 14), (120 + num_of_frames - 14));
|
|
else if (num_of_frames < 23)
|
|
set_rx_bd_empty((120 + num_of_frames - 18), (120 + num_of_frames - 18));
|
|
else if (num_of_frames < 28)
|
|
set_rx_bd_empty((120 + num_of_frames - 23), (120 + num_of_frames - 23));
|
|
else if (num_of_frames < 34)
|
|
set_rx_bd_empty((120 + num_of_frames - 28), (120 + num_of_frames - 28));
|
|
else if (num_of_frames < 40)
|
|
set_rx_bd_empty((120 + num_of_frames - 34), (120 + num_of_frames - 34));
|
|
else if (num_of_frames < 47)
|
|
set_rx_bd_empty((120 + num_of_frames - 40), (120 + num_of_frames - 40));
|
|
else if (num_of_frames < 54)
|
|
set_rx_bd_empty((120 + num_of_frames - 47), (120 + num_of_frames - 47));
|
|
else if (num_of_frames < 62)
|
|
set_rx_bd_empty((120 + num_of_frames - 54), (120 + num_of_frames - 54));
|
|
else if (num_of_frames < 70)
|
|
set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
|
|
else if (num_of_frames < 78)
|
|
set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
|
|
// CHECK END OF RECEIVE
|
|
// receive just preamble between some packets
|
|
if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
|
|
@(posedge mrx_clk);
|
|
wait (MRxDV === 1'b0); // end receive
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(15) @(posedge wb_clk);
|
|
end
|
|
// receiving frames and checking end of them
|
|
frame_ended = 0;
|
|
check_frame = 0;
|
|
fork
|
|
begin
|
|
if (i_length[0] == 1'b0)
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
else
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin: fr_end1
|
|
wait (MRxDV === 1'b1); // start receive
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
test_fail("Wrong buffer descriptor's empty bit read out from MAC");
|
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MRxDV === 1'b0); // end receive
|
wait (MRxDV === 1'b0); // end transmit
|
while ((data[15] === 1) && (check_frame == 0))
|
while (data[15] === 1)
|
begin
|
begin
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(num_of_bd, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
if (data[15] === 0)
|
|
frame_ended = 1;
|
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
begin
|
|
wait (MRxDV === 1'b1); // start receive
|
|
wait (MRxDV === 1'b0); // end receive
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(15) @(posedge wb_clk);
|
|
check_frame = 1;
|
|
end
|
end
|
join
|
join
|
// check length of a PACKET
|
// check length of a PACKET
|
if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
|
if (data[31:16] != (i_length + 4))
|
((data[31:16] != 0) && (num_of_frames < 3)) )
|
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
data[31:16], (i_length + 4));
|
data[31:16], (i_length + 4));
|
test_fail("Wrong length of the packet out from PHY");
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check received RX packet data and CRC
|
// check received RX packet data and CRC
|
if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
|
|
begin // CRC has 4 bytes for itself
|
|
if (i_length[0] == 1'b0)
|
if (i_length[0] == 1'b0)
|
begin
|
begin
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
end
|
end
|
else
|
else
|
| Line 14083... |
Line 14191... |
begin
|
begin
|
`TIME; $display("*E Wrong data of the received packet");
|
`TIME; $display("*E Wrong data of the received packet");
|
test_fail("Wrong data of the received packet");
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
|
// check WB INT signal
|
// check WB INT signal
|
if (num_of_frames >= 3) // Frames smaller than 3 are not received.
|
if (i_length[1:0] == 2'h0)
|
begin // Frames greater then 5 always cause an interrupt (Frame received)
|
begin
|
if (wb_int !== 1'b1) // Frames with length 3 or 4 always cause an interrupt (CRC error)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 14104... |
Line 14211... |
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
check_rx_bd(num_of_bd, data);
|
if (num_of_frames >= min_tmp)
|
if (i_length[1] == 1'b0) // interrupt enabled
|
begin
|
|
if ( (data[15:0] !== 16'h6080) && // wrap bit
|
|
(data[15:0] !== 16'h4080) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames > 6)
|
|
begin
|
|
if ( (data[15:0] !== 16'h6084) && // wrap bit
|
|
(data[15:0] !== 16'h4084) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
|
|
begin
|
|
if ( (data[15:0] !== 16'h6084) && // wrap bit
|
|
(data[15:0] !== 16'h4084) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
|
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6086) && // wrap bit
|
if ( ((data[15:0] !== 16'h6080) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
|
(data[15:0] !== 16'h4086) ) // without wrap bit
|
((data[15:0] !== 16'h4080) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else
|
else // interrupt not enabled
|
begin
|
begin
|
if (data[15] !== 1'b1)
|
if ( ((data[15:0] !== 16'h2080) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
|
|
((data[15:0] !== 16'h0080) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
|
// clear first half of 8 frames from RX buffer descriptor 0
|
|
if (num_of_frames < 4)
|
|
clear_rx_bd(num_of_bd, num_of_bd);
|
|
// clear BD with wrap bit
|
|
if (num_of_frames == 140)
|
|
clear_rx_bd(127, 127);
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (num_of_frames >= 5)
|
if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
|
begin
|
begin
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Receive Buffer was not set");
|
test_fail("Interrupt Receive Buffer was not set");
|
| Line 14172... |
Line 14256... |
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
|
|
begin
|
|
if (data) // Checking if any interrupt is pending)
|
|
begin
|
|
`TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
|
|
test_fail("Interrupts were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
else
|
begin
|
begin
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
if (data !== 0)
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 14206... |
Line 14275... |
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
if (num_of_frames == 3)
|
if ((i_length + 4) == (min_tmp + 7))
|
begin
|
begin
|
$display(" using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
|
// starting length is min_tmp, ending length is (min_tmp + 128)
|
$display(" ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
|
$display(" receive small packets is NOT selected");
|
0, 3);
|
$display(" using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)");
|
|
$display(" ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
|
|
min_tmp, (min_tmp + 7));
|
|
$display(" ->all packets were received on RX BD 0");
|
|
// reset receive small, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if (num_of_frames == 9)
|
else if ((i_length + 4) == (min_tmp + 128))
|
begin
|
begin
|
$display(" using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
|
// starting length is min_tmp, ending length is (min_tmp + 128)
|
$display(" ->packet with length 4 is not received (length increasing by 1 byte)");
|
$display(" receive small packets is NOT selected");
|
|
$display(" using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
5, 9);
|
(min_tmp + 8), (min_tmp + 128));
|
|
$display(" ->packets were received on RX BD %0d to RX BD %0d respectively",
|
|
1'b0, num_of_bd);
|
|
tmp_bd = num_of_bd + 1;
|
|
// set receive small, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if (num_of_frames == 17)
|
else if ((i_length + 4) == (max_tmp - 16))
|
begin
|
begin
|
$display(" using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
|
// starting length is for +128 longer than previous ending length, while ending length is tmp_data
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
$display(" receive small packets is selected");
|
10, 17);
|
$display(" using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
|
|
(min_tmp + 64 + 128), tmp_data);
|
|
if (tmp_bd > num_of_bd)
|
|
$display(" ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
|
|
tmp_bd, num_of_bd);
|
|
else
|
|
$display(" ->packets were received from RX BD %0d to RX BD %0d respectively",
|
|
tmp_bd, num_of_bd);
|
|
tmp_bd = num_of_bd + 1;
|
|
// reset receive small, remain the rest
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if (num_of_frames == 27)
|
else if ((i_length + 4) == max_tmp)
|
begin
|
begin
|
$display(" using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
|
$display(" receive small packets is NOT selected");
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
$display(" using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
|
18, 27);
|
$display(" ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
|
|
(max_tmp - (4 + 16)), max_tmp);
|
|
if (tmp_bd > num_of_bd)
|
|
$display(" ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
|
|
tmp_bd, num_of_bd);
|
|
else
|
|
$display(" ->packets were received from RX BD %0d to RX BD %0d respectively",
|
|
tmp_bd, num_of_bd);
|
end
|
end
|
else if (num_of_frames == 40)
|
// set length (loop variable)
|
|
if ((i_length + 4) < (min_tmp + 128))
|
|
i_length = i_length + 1;
|
|
else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
|
|
i_length = 256;
|
|
else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
|
begin
|
begin
|
$display(" using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
|
i_length = i_length + 128;
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
tmp_data = i_length + 4; // last tmp_data is ending length
|
28, 40);
|
|
end
|
|
else if (num_of_frames == 54)
|
|
begin
|
|
$display(" using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
41, 54);
|
|
end
|
|
else if (num_of_frames == 69)
|
|
begin
|
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
55, 69);
|
|
end
|
|
else if (num_of_frames == 69)
|
|
begin
|
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
55, 69);
|
|
end
|
end
|
else if (num_of_frames == 77)
|
else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
|
|
i_length = max_tmp - (4 + 16);
|
|
else if ((i_length + 4) >= (max_tmp - 16))
|
|
i_length = i_length + 1;
|
|
else
|
begin
|
begin
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
$display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
#10 $stop;
|
70, 77);
|
|
end
|
end
|
// set length (loop variable)
|
|
i_length = i_length + 1;
|
|
// the number of frame transmitted
|
// the number of frame transmitted
|
num_of_frames = num_of_frames + 1;
|
num_of_frames = num_of_frames + 1;
|
if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
|
if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
|
(num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
|
num_of_bd = 0;
|
(num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
|
|
(num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
|
|
num_of_bd = 120;
|
|
else
|
else
|
num_of_bd = num_of_bd + 1;
|
num_of_bd = num_of_bd + 1;
|
end
|
end
|
// disable RX
|
// disable RX
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
| Line 14287... |
Line 14379... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets form 0 to (MINFL + 12) sizes at ////
|
//// Test receive packets from 0 to (MINFL + 12) sizes at ////
|
//// 8 RX buffer decriptors ( 100Mbps ). ////
|
//// 8 RX buffer decriptors ( 10Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 9) //
|
if (test_num == 8) //
|
begin
|
begin
|
// TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )
|
// TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )
|
test_name = "TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )";
|
test_name = "TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )";
|
`TIME; $display(" TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )");
|
`TIME; $display(" TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )");
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 14324... |
Line 14416... |
// unmask interrupts
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 10;
|
|
|
frame_ended = 0;
|
frame_ended = 0;
|
num_of_frames = 0;// 0; // 10;
|
num_of_frames = 0;// 0; // 10;
|
num_of_bd = 120;
|
num_of_bd = 120;
|
i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
|
i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
|
| Line 14563... |
Line 14655... |
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
else
|
else
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
end
|
end
|
begin: fr_end2
|
begin: fr_end1
|
wait (MRxDV === 1'b1); // start receive
|
wait (MRxDV === 1'b1); // start receive
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(num_of_bd, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's empty bit read out from MAC");
|
test_fail("Wrong buffer descriptor's empty bit read out from MAC");
|
| Line 14636... |
Line 14728... |
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
|
// check RX buffer descriptor of a packet
|
if (num_of_frames >= min_tmp)
|
if (num_of_frames >= min_tmp)
|
begin
|
begin
|
if ( (data[15:0] !== 16'h6080) && // wrap bit
|
if ( (data[15:0] !== 16'h6080) && // wrap bit
|
(data[15:0] !== 16'h4080) ) // without wrap bit
|
(data[15:0] !== 16'h4080) ) // without wrap bit
|
begin
|
begin
|
| Line 14818... |
Line 14911... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets at one RX BD and ////
|
//// Test receive packets from 0 to (MINFL + 12) sizes at ////
|
//// check addresses ( 10Mbps ). ////
|
//// 8 RX buffer decriptors ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 10) //
|
if (test_num == 9) //
|
begin
|
begin
|
// TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )
|
// TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )
|
test_name = "TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )";
|
test_name = "TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )";
|
`TIME; $display(" TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )");
|
`TIME; $display(" TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )");
|
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// unmask interrupts
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// prepare two packets of MAXFL length
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
|
|
min_tmp = tmp[31:16];
|
|
st_data = 8'hAC;
|
|
set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
st_data = 8'h35;
|
|
set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 100;
|
|
|
num_of_frames = 0;
|
frame_ended = 0;
|
i_length = 64;
|
num_of_frames = 0;// 0; // 10;
|
while (num_of_frames < 8)
|
num_of_bd = 120;
|
|
i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
|
|
while ((i_length + 4) < 78) // (min_tmp - 4))
|
|
begin
|
|
// append CRC to packet
|
|
if ((i_length[0] == 1'b0) && (num_of_frames > 4))
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
else if (num_of_frames > 4)
|
|
append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
|
|
// choose generating carrier sense and collision
|
|
case (i_length[1:0])
|
|
2'h0:
|
begin
|
begin
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
case (num_of_frames)
|
end
|
0: // unicast + PRO
|
2'h1:
|
begin
|
begin
|
// enable interrupt generation
|
// detect carrier sense in FD and no collision
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
eth_phy.collision(0);
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet is going to be received with PRO bit (wrap at 1st BD)");
|
|
end
|
end
|
1: // unicast
|
2'h2:
|
begin
|
begin
|
// enable interrupt generation
|
// not detect carrier sense in FD and set collision
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
eth_phy.collision(1);
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h12;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet is going to be received without PRO bit (wrap at 1st BD)");
|
|
end
|
end
|
2: // wrong unicast + PRO
|
default: // 2'h3:
|
begin
|
begin
|
// enable interrupt generation
|
// detect carrier sense in FD and set collision
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
eth_phy.no_carrier_sense_rx_fd_detect(1);
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
eth_phy.collision(1);
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h31;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet is going to be received with PRO bit (wrap at 1st BD)");
|
|
end
|
end
|
3: // wrong unicast
|
endcase
|
|
#1;
|
|
// first 10 frames are received with RX BD 120 (wrap bit on RX BD 120)
|
|
if (num_of_frames <= 9)
|
|
begin
|
|
case (i_length[1:0])
|
|
2'h0: // Interrupt is generated
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD)");
|
|
end
|
end
|
4: // broadcast + PRO + ~BRO
|
2'h1: // Interrupt is generated
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h84;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
end
|
5: // broadcast + ~BRO
|
2'h2: // Interrupt is generated
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h48;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
6: // broadcast + PRO + BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h30;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
end
|
7: // broadcast + BRO
|
default: // 2'h3: // Interrupt is generated
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h04;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
default:
|
|
begin
|
|
end
|
end
|
endcase
|
endcase
|
// set wrap bit
|
// set wrap bit
|
set_rx_bd_wrap(127);
|
set_rx_bd_wrap(120);
|
set_rx_bd_empty(127, 127);
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
end
|
begin: wait_for_rec0
|
// 10 <= num_of_frames < 18 => wrap set to TX BD 123
|
wait (MRxDV === 1'b1); // start transmit
|
else if ((num_of_frames == 10) || (num_of_frames == 14))
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
tmp_len = i_length; // length of frame
|
fail = fail + 1;
|
tmp_bd_num = 120; // RX BD number
|
end
|
while (tmp_bd_num < 124) //
|
wait (MRxDV === 1'b0); // end transmit
|
|
while (data[15] === 1)
|
|
begin
|
begin
|
#1 check_rx_bd(127, data);
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
@(posedge wb_clk);
|
if (tmp_len[0] == 0)
|
end
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
disable check_wait_for_rec0;
|
else
|
$display(" ->packet received");
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
repeat (1) @(posedge wb_clk);
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
begin: check_wait_for_rec0
|
// set wrap bit
|
wait (MRxDV === 1'b1); // start transmit
|
set_rx_bd_wrap(123);
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(50) @(posedge wb_clk);
|
|
wait (wbm_working == 0);
|
|
disable wait_for_rec0;
|
|
$display(" ->packet NOT received");
|
|
end
|
end
|
join
|
// 18 <= num_of_frames < 28 => wrap set to RX BD 124
|
// PACKET checking
|
else if ((num_of_frames == 18) || (num_of_frames == 23))
|
wait (wbm_working == 0);
|
|
check_rx_bd(127, data);
|
|
case (num_of_frames)
|
|
0, 1, 4, 5:
|
|
begin
|
begin
|
// check WB INT signal
|
tmp_len = i_length; // length of frame
|
if (wb_int !== 1'b1)
|
tmp_bd_num = 120; // RX BD number
|
|
while (tmp_bd_num < 125) //
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
test_fail("WB INT signal should be set");
|
if (tmp_len[0] == 0)
|
fail = fail + 1;
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// check RX buffer descriptor of a packet
|
// set wrap bit
|
if (data[15:0] !== 16'h6000)
|
set_rx_bd_wrap(124);
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
end
|
// check length of a PACKET
|
// 28 <= num_of_frames < 40 => wrap set to RX BD 125
|
if (data[31:16] != (i_length + 4))
|
else if ((num_of_frames == 28) || (num_of_frames == 34))
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
tmp_len = i_length; // length of frame
|
data[31:16], (i_length + 4));
|
tmp_bd_num = 120; // RX BD number
|
test_fail("Wrong length of the packet out from PHY");
|
while (tmp_bd_num < 126) //
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
begin
|
`TIME; $display("*E Wrong data of the received packet");
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
test_fail("Wrong data of the received packet");
|
if (tmp_len[0] == 0)
|
fail = fail + 1;
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// check interrupts
|
// set wrap bit
|
wait (wbm_working == 0);
|
set_rx_bd_wrap(125);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
end
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
// 40 <= num_of_frames < 54 => wrap set to RX BD 126
|
|
else if ((num_of_frames == 40) || (num_of_frames == 47))
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
tmp_len = i_length; // length of frame
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
tmp_bd_num = 120; // RX BD number
|
fail = fail + 1;
|
while (tmp_bd_num < 127) //
|
|
begin
|
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
|
if (tmp_len[0] == 0)
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
|
// set wrap bit
|
|
set_rx_bd_wrap(126);
|
end
|
end
|
2, 6:
|
// 54 <= num_of_frames < 70 => wrap set to RX BD 127
|
|
else if ((num_of_frames == 54) || (num_of_frames == 62))
|
begin
|
begin
|
// check WB INT signal
|
tmp_len = i_length; // length of frame
|
if (wb_int !== 1'b1)
|
tmp_bd_num = 120; // RX BD number
|
|
while (tmp_bd_num < 128) //
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
test_fail("WB INT signal should be set");
|
if (tmp_len[0] == 0)
|
fail = fail + 1;
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
|
else
|
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
|
tmp_len = tmp_len + 1;
|
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
end
|
end
|
// check RX buffer descriptor of a packet
|
// set wrap bit
|
if (data[15:0] !== 16'h6080)
|
set_rx_bd_wrap(127);
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
end
|
// check length of a PACKET
|
// 70 <= num_of_frames < 78 => wrap set to RX BD 127
|
if (data[31:16] != (i_length + 4))
|
else if (num_of_frames == 70)
|
begin
|
begin
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
tmp_len = i_length; // length of frame
|
data[31:16], (i_length + 4));
|
tmp_bd_num = 120; // RX BD number
|
test_fail("Wrong length of the packet out from PHY");
|
while (tmp_bd_num < 128) //
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
begin
|
`TIME; $display("*E Wrong data of the received packet");
|
// if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
|
test_fail("Wrong data of the received packet");
|
if (tmp_len[0] == 0)
|
fail = fail + 1;
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
|
end
|
else
|
// check interrupts
|
set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
|
wait (wbm_working == 0);
|
// set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
tmp_len = tmp_len + 1;
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
// set RX BD number
|
|
tmp_bd_num = tmp_bd_num + 1;
|
|
end
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
end
|
|
#1;
|
|
// SET empty bit
|
|
if (num_of_frames < 10)
|
|
set_rx_bd_empty(120, 120);
|
|
else if (num_of_frames < 14)
|
|
set_rx_bd_empty((120 + num_of_frames - 10), (120 + num_of_frames - 10));
|
|
else if (num_of_frames < 18)
|
|
set_rx_bd_empty((120 + num_of_frames - 14), (120 + num_of_frames - 14));
|
|
else if (num_of_frames < 23)
|
|
set_rx_bd_empty((120 + num_of_frames - 18), (120 + num_of_frames - 18));
|
|
else if (num_of_frames < 28)
|
|
set_rx_bd_empty((120 + num_of_frames - 23), (120 + num_of_frames - 23));
|
|
else if (num_of_frames < 34)
|
|
set_rx_bd_empty((120 + num_of_frames - 28), (120 + num_of_frames - 28));
|
|
else if (num_of_frames < 40)
|
|
set_rx_bd_empty((120 + num_of_frames - 34), (120 + num_of_frames - 34));
|
|
else if (num_of_frames < 47)
|
|
set_rx_bd_empty((120 + num_of_frames - 40), (120 + num_of_frames - 40));
|
|
else if (num_of_frames < 54)
|
|
set_rx_bd_empty((120 + num_of_frames - 47), (120 + num_of_frames - 47));
|
|
else if (num_of_frames < 62)
|
|
set_rx_bd_empty((120 + num_of_frames - 54), (120 + num_of_frames - 54));
|
|
else if (num_of_frames < 70)
|
|
set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
|
|
else if (num_of_frames < 78)
|
|
set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
|
|
// CHECK END OF RECEIVE
|
|
// receive just preamble between some packets
|
|
if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
|
test_fail("Interrupt Receive Buffer was not set");
|
@(posedge mrx_clk);
|
|
wait (MRxDV === 1'b0); // end receive
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(15) @(posedge wb_clk);
|
|
end
|
|
// receiving frames and checking end of them
|
|
frame_ended = 0;
|
|
check_frame = 0;
|
|
fork
|
|
begin
|
|
if (i_length[0] == 1'b0)
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
else
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin: fr_end2
|
|
wait (MRxDV === 1'b1); // start receive
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
test_fail("Wrong buffer descriptor's empty bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
wait (MRxDV === 1'b0); // end receive
|
|
while ((data[15] === 1) && (check_frame == 0))
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
#1 check_rx_bd(num_of_bd, data);
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
@(posedge wb_clk);
|
|
end
|
|
if (data[15] === 0)
|
|
frame_ended = 1;
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
begin
|
|
wait (MRxDV === 1'b1); // start receive
|
|
wait (MRxDV === 1'b0); // end receive
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(15) @(posedge wb_clk);
|
|
check_frame = 1;
|
|
end
|
|
join
|
|
// check length of a PACKET
|
|
if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
|
|
((data[31:16] != 0) && (num_of_frames < 3)) )
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// check received RX packet data and CRC
|
|
if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
|
|
begin // CRC has 4 bytes for itself
|
|
if (i_length[0] == 1'b0)
|
|
begin
|
|
check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
|
end
|
end
|
3, 7:
|
else
|
begin
|
begin
|
|
check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
|
|
end
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
// check WB INT signal
|
// check WB INT signal
|
|
if (num_of_frames >= 3) // Frames smaller than 3 are not received.
|
|
begin // Frames greater then 5 always cause an interrupt (Frame received)
|
|
if (wb_int !== 1'b1) // Frames with length 3 or 4 always cause an interrupt (CRC error)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (data[15:0] !== 16'hE000)
|
if (num_of_frames >= min_tmp)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
if ( (data[15:0] !== 16'h6080) && // wrap bit
|
|
(data[15:0] !== 16'h4080) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames > 6)
|
|
begin
|
|
if ( (data[15:0] !== 16'h6084) && // wrap bit
|
|
(data[15:0] !== 16'h4084) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
|
|
begin
|
|
if ( (data[15:0] !== 16'h6084) && // wrap bit
|
|
(data[15:0] !== 16'h4084) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
|
|
begin
|
|
if ( (data[15:0] !== 16'h6086) && // wrap bit
|
|
(data[15:0] !== 16'h4086) ) // without wrap bit
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (data[15] !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (data !== 0)
|
if (num_of_frames >= 5)
|
begin
|
begin
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
default:
|
|
begin
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
end
|
end
|
endcase
|
end
|
// clear RX buffer descriptor
|
else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
|
clear_rx_bd(127, 127);
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
if (data) // Checking if any interrupt is pending)
|
|
begin
|
|
`TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
|
|
test_fail("Interrupts were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
num_of_frames = num_of_frames + 1;
|
|
end
|
end
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
else
|
fail = 0;
|
begin
|
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
end
|
end
|
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packets at one RX BD and ////
|
|
//// check addresses ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 11) //
|
|
begin
|
begin
|
// TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
test_name = "TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )";
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
`TIME; $display(" TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )");
|
fail = fail + 1;
|
|
end
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
end
|
wait (wbm_working == 0);
|
// clear interrupts
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// INTERMEDIATE DISPLAYS
|
// write to phy's control register for 100Mbps
|
if (num_of_frames == 3)
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 100;
|
|
|
|
num_of_frames = 0;
|
|
i_length = 64;
|
|
while (num_of_frames < 8)
|
|
begin
|
begin
|
// not detect carrier sense in FD and no collision
|
$display(" using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
$display(" ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
|
|
0, 3);
|
|
end
|
|
else if (num_of_frames == 9)
|
|
begin
|
|
$display(" using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
|
|
$display(" ->packet with length 4 is not received (length increasing by 1 byte)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
5, 9);
|
|
end
|
|
else if (num_of_frames == 17)
|
|
begin
|
|
$display(" using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
10, 17);
|
|
end
|
|
else if (num_of_frames == 27)
|
|
begin
|
|
$display(" using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
18, 27);
|
|
end
|
|
else if (num_of_frames == 40)
|
|
begin
|
|
$display(" using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
28, 40);
|
|
end
|
|
else if (num_of_frames == 54)
|
|
begin
|
|
$display(" using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
41, 54);
|
|
end
|
|
else if (num_of_frames == 69)
|
|
begin
|
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
55, 69);
|
|
end
|
|
else if (num_of_frames == 69)
|
|
begin
|
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
55, 69);
|
|
end
|
|
else if (num_of_frames == 77)
|
|
begin
|
|
$display(" using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
|
|
$display(" ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
|
|
70, 77);
|
|
end
|
|
// set length (loop variable)
|
|
i_length = i_length + 1;
|
|
// the number of frame transmitted
|
|
num_of_frames = num_of_frames + 1;
|
|
if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
|
|
(num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
|
|
(num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
|
|
(num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
|
|
num_of_bd = 120;
|
|
else
|
|
num_of_bd = num_of_bd + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
@(posedge wb_clk);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packets at one RX BD and ////
|
|
//// check addresses ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 10) //
|
|
begin
|
|
// TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )
|
|
test_name = "TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )";
|
|
`TIME; $display(" TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )");
|
|
|
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// write to phy's control register for 10Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 10;
|
|
|
|
num_of_frames = 0;
|
|
i_length = 64;
|
|
while (num_of_frames < 8)
|
|
begin
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
case (num_of_frames)
|
case (num_of_frames)
|
0: // unicast + PRO
|
0: // unicast + PRO
|
begin
|
begin
|
// enable interrupt generation
|
// enable interrupt generation
|
| Line 15483... |
Line 15682... |
fork
|
fork
|
begin
|
begin
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
end
|
end
|
begin: wait_for_rec1
|
begin: wait_for_rec0
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
#1 check_rx_bd(127, data);
|
#1 check_rx_bd(127, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
| Line 15497... |
Line 15696... |
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
#1 check_rx_bd(127, data);
|
#1 check_rx_bd(127, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
disable check_wait_for_rec1;
|
disable check_wait_for_rec0;
|
$display(" ->packet received");
|
$display(" ->packet received");
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
begin: check_wait_for_rec1
|
begin: check_wait_for_rec0
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b0); // end transmit
|
wait (MRxDV === 1'b0); // end transmit
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
repeat(50) @(posedge wb_clk);
|
repeat(50) @(posedge wb_clk);
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
disable wait_for_rec1;
|
disable wait_for_rec0;
|
$display(" ->packet NOT received");
|
$display(" ->packet NOT received");
|
end
|
end
|
join
|
join
|
// PACKET checking
|
// PACKET checking
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 15668... |
Line 15867... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets at 8 RX BD with ////
|
//// Test receive packets at one RX BD and ////
|
//// RX FIFO and RX BD overrun ( 10Mbps ). ////
|
//// check addresses ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 12) //
|
if (test_num == 11) //
|
begin
|
begin
|
// TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )
|
// TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )
|
test_name = "TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )";
|
test_name = "TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )";
|
`TIME; $display(" TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )");
|
`TIME; $display(" TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )");
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 10;
|
speed = 100;
|
|
|
// enable interrupt generation
|
|
set_rx_bd(120, 127, 1'b1, `MEMORY_BASE);
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
num_of_frames = 0;
|
num_of_frames = 0;
|
while (num_of_frames < 11)
|
i_length = 64;
|
|
while (num_of_frames < 8)
|
begin
|
begin
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
if (num_of_frames < 2)
|
|
num_of_bd = 120 + num_of_frames;
|
|
else if (num_of_frames < 9)
|
|
num_of_bd = 120 + num_of_frames - 1;
|
|
else
|
|
num_of_bd = 120;
|
|
case (num_of_frames)
|
case (num_of_frames)
|
0:
|
0: // unicast + PRO
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
// prepare packet
|
// prepare packet
|
i_length = 60;
|
|
st_data = 8'h0F;
|
st_data = 8'h0F;
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet is going to be received with PRO bit (wrap at 1st BD)");
|
end
|
end
|
3:
|
1: // unicast
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
// prepare packet
|
// prepare packet
|
i_length = 68;
|
st_data = 8'h12;
|
st_data = 8'h01;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet is going to be received without PRO bit (wrap at 1st BD)");
|
end
|
end
|
6:
|
2: // wrong unicast + PRO
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
// prepare packet
|
// prepare packet
|
i_length = 80;
|
st_data = 8'h31;
|
st_data = 8'hA1;
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet is going to be received with PRO bit (wrap at 1st BD)");
|
end
|
end
|
10:
|
3: // wrong unicast
|
begin
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
end
|
|
default:
|
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD)");
|
end
|
end
|
endcase
|
4: // broadcast + PRO + ~BRO
|
// DISPLAYS
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
begin
|
$display(" packet shoud be successfuly received");
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h84;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)");
|
end
|
end
|
1: // correct packet stayed in RX FIFO
|
5: // broadcast + ~BRO
|
begin
|
begin
|
$display(" packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun");
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h48;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD)");
|
end
|
end
|
2, 4, 6: // RX FIFO overrun
|
6: // broadcast + PRO + BRO
|
begin
|
begin
|
$display(" packet should NOT be received - RX FIFO overrun");
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h30;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)");
|
end
|
end
|
9: // RX BD overrun
|
7: // broadcast + BRO
|
begin
|
begin
|
$display(" packet should NOT be received - RX FIFO overrun due to lack of RX BDs");
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h04;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD)");
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
end
|
end
|
endcase
|
endcase
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
fork
|
fork
|
begin
|
begin
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
end
|
end
|
begin: set_no_resp2
|
begin: wait_for_rec1
|
if ((num_of_frames == 1) || (num_of_frames == 4)) // RX FIFO overrun!
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
if (num_of_frames == 6) // RX FIFO overrun!
|
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (eth_ma_wb_ack_i === 1'b1) // WB transfer
|
|
wait (eth_ma_wb_ack_i === 1'b0) // WB transfer
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
end
|
|
end
|
|
begin: wait_for_rec2
|
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(127, data);
|
//$display("Num of RX BD = %d, RX BD %0d = %h", num_of_bd, num_of_bd, data);
|
if (data[15] !== 1)
|
if (((data[15] !== 1) && (num_of_frames != 9)) || // RX BD must be Empty
|
|
((data[15] !== 0) && (num_of_frames == 9))) // RX BD must NOT be Empty - RX BD overrun!!!
|
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MRxDV === 1'b0); // end transmit
|
wait (MRxDV === 1'b0); // end transmit
|
while (((data[15] === 1) && (num_of_frames != 9)) ||
|
while (data[15] === 1)
|
((data[15] === 0) && (num_of_frames == 9)))
|
|
begin
|
begin
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(127, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
disable check_wait_for_rec2;
|
disable check_wait_for_rec1;
|
disable set_no_resp2;
|
|
$display(" ->packet received");
|
$display(" ->packet received");
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
begin: check_wait_for_rec2
|
begin: check_wait_for_rec1
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b0); // end transmit
|
wait (MRxDV === 1'b0); // end transmit
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
repeat(50) @(posedge wb_clk);
|
repeat(50) @(posedge wb_clk);
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
disable wait_for_rec2;
|
disable wait_for_rec1;
|
disable set_no_resp2;
|
|
$display(" ->packet NOT received");
|
$display(" ->packet NOT received");
|
end
|
end
|
join
|
join
|
// PACKET checking
|
// PACKET checking
|
|
wait (wbm_working == 0);
|
|
check_rx_bd(127, data);
|
case (num_of_frames)
|
case (num_of_frames)
|
0, 3, 5, 7, 8, 10: // correct packet received
|
0, 1, 4, 5:
|
begin
|
begin
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (((data[15:0] !== 16'h4000) && (num_of_bd != 127)) || // without wrap bit
|
if (data[15:0] !== 16'h6000)
|
((data[15:0] !== 16'h6000) && (num_of_bd == 127)))
|
|
begin
|
begin
|
`TIME;
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
if (num_of_bd != 127)
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 6000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check length of a PACKET
|
// check length of a PACKET
|
if (data[31:16] != (i_length + 4))
|
if (data[31:16] != (i_length + 4))
|
| Line 15923... |
Line 16187... |
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
1: // correct packet stayed in RX FIFO
|
2, 6:
|
begin
|
begin
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (data[15:0] !== 16'hC000)
|
if (data[15:0] !== 16'h6080)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (data !== 0)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
2: // RX FIFO overrun & previous packet written
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
3, 7:
|
begin
|
begin
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (data[15:0] !== 16'hC000)
|
if (data[15:0] !== 16'hE000)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 16012... |
Line 16260... |
begin
|
begin
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// clear RX buffer descriptor
|
|
clear_rx_bd(127, 127);
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
////////////////////////////////////////////////////////////////////
|
repeat(128) @(posedge wb_clk);
|
//// ////
|
$display(" ->previous packet written into MEM");
|
//// Test receive packets at 8 RX BD with ////
|
|
//// RX FIFO and RX BD overrun ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 12) //
|
|
begin
|
|
// TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )
|
|
test_name = "TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )";
|
|
`TIME; $display(" TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )");
|
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 10Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 10;
|
|
|
|
// enable interrupt generation
|
|
set_rx_bd(120, 127, 1'b1, `MEMORY_BASE);
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
|
//check_rx_bd(120, data);
|
//check_rx_bd(120, data);
|
//$display("RX BD 120 = %h", data);
|
//$display("RX BD 120 = %h", data);
|
//check_rx_bd(121, data);
|
//check_rx_bd(121, data);
|
//$display("RX BD 121 = %h", data);
|
//$display("RX BD 121 = %h", data);
|
| Line 16035... |
Line 16355... |
//check_rx_bd(126, data);
|
//check_rx_bd(126, data);
|
//$display("RX BD 126 = %h", data);
|
//$display("RX BD 126 = %h", data);
|
//check_rx_bd(127, data);
|
//check_rx_bd(127, data);
|
//$display("RX BD 127 = %h", data);
|
//$display("RX BD 127 = %h", data);
|
|
|
// check WB INT signal
|
num_of_frames = 0;
|
if (wb_int !== 1'b1)
|
while (num_of_frames < 11)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
// not detect carrier sense in FD and no collision
|
test_fail("WB INT signal should be set");
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
fail = fail + 1;
|
eth_phy.collision(0);
|
|
if (num_of_frames < 2)
|
|
num_of_bd = 120 + num_of_frames;
|
|
else if (num_of_frames < 9)
|
|
num_of_bd = 120 + num_of_frames - 1;
|
|
else
|
|
num_of_bd = 120;
|
|
case (num_of_frames)
|
|
0:
|
|
begin
|
|
// prepare packet
|
|
i_length = 60;
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
3:
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4000)
|
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
// prepare packet
|
test_fail("RX buffer descriptor status is not correct");
|
i_length = 68;
|
fail = fail + 1;
|
st_data = 8'h01;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
end
|
end
|
// check interrupts
|
6:
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
// prepare packet
|
test_fail("Interrupt Receive Buffer Error was not set");
|
i_length = 80;
|
fail = fail + 1;
|
st_data = 8'hA1;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
end
|
end
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
10:
|
|
begin
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// DISPLAYS
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
$display(" packet shoud be successfuly received");
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
$display(" packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun");
|
|
end
|
|
2, 4, 6: // RX FIFO overrun
|
|
begin
|
|
$display(" packet should NOT be received - RX FIFO overrun");
|
|
end
|
|
9: // RX BD overrun
|
|
begin
|
|
$display(" packet should NOT be received - RX FIFO overrun due to lack of RX BDs");
|
|
end
|
|
default:
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
end
|
|
endcase
|
|
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
end
|
end
|
4, 6: // RX FIFO overrun
|
begin: set_no_resp2
|
|
if ((num_of_frames == 1) || (num_of_frames == 4)) // RX FIFO overrun!
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
if (num_of_frames == 6) // RX FIFO overrun!
|
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (eth_ma_wb_ack_i === 1'b1) // WB transfer
|
|
wait (eth_ma_wb_ack_i === 1'b0) // WB transfer
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
end
|
|
end
|
|
begin: wait_for_rec2
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
//$display("Num of RX BD = %d, RX BD %0d = %h", num_of_bd, num_of_bd, data);
|
|
if (((data[15] !== 1) && (num_of_frames != 9)) || // RX BD must be Empty
|
|
((data[15] !== 0) && (num_of_frames == 9))) // RX BD must NOT be Empty - RX BD overrun!!!
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
while (((data[15] === 1) && (num_of_frames != 9)) ||
|
|
((data[15] === 0) && (num_of_frames == 9)))
|
|
begin
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
disable check_wait_for_rec2;
|
|
disable set_no_resp2;
|
|
$display(" ->packet received");
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
begin: check_wait_for_rec2
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(50) @(posedge wb_clk);
|
|
wait (wbm_working == 0);
|
|
disable wait_for_rec2;
|
|
disable set_no_resp2;
|
|
$display(" ->packet NOT received");
|
|
end
|
|
join
|
|
// PACKET checking
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
begin
|
begin
|
|
|
//check_rx_bd(120, data);
|
//check_rx_bd(120, data);
|
//$display("RX BD 120 = %h", data);
|
//$display("RX BD 120 = %h", data);
|
//check_rx_bd(121, data);
|
//check_rx_bd(121, data);
|
| Line 16088... |
Line 16496... |
//$display("RX BD 126 = %h", data);
|
//$display("RX BD 126 = %h", data);
|
//check_rx_bd(127, data);
|
//check_rx_bd(127, data);
|
//$display("RX BD 127 = %h", data);
|
//$display("RX BD 127 = %h", data);
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (((data[15:0] !== 16'h4000) && (num_of_bd != 127)) || // without wrap bit
|
|
((data[15:0] !== 16'h6000) && (num_of_bd == 127)))
|
|
begin
|
|
`TIME;
|
|
if (num_of_bd != 127)
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 6000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
2: // RX FIFO overrun & previous packet written
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
$display(" ->previous packet written into MEM");
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
end
|
|
4, 6: // RX FIFO overrun
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4040)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4040", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
end
|
|
9: // RX BD overrun
|
|
begin
|
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
// NOT checked since BD value is from first packet - RX BD overrun
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_BUSY) !== `ETH_INT_BUSY)
|
|
begin
|
|
`TIME; $display("*E Interrupt BUSY was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt BUSY was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_BUSY)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except BUSY) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except BUSY) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packets at 8 RX BD with ////
|
|
//// RX FIFO and RX BD overrun ( 100Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 13) //
|
|
begin
|
|
// TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )
|
|
test_name = "TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )";
|
|
`TIME; $display(" TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )");
|
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 100Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 100;
|
|
|
|
// enable interrupt generation
|
|
set_rx_bd(120, 127, 1'b1, `MEMORY_BASE);
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
|
|
num_of_frames = 0;
|
|
while (num_of_frames < 11)
|
|
begin
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
if (num_of_frames < 2)
|
|
num_of_bd = 120 + num_of_frames;
|
|
else if (num_of_frames < 9)
|
|
num_of_bd = 120 + num_of_frames - 1;
|
|
else
|
|
num_of_bd = 120;
|
|
case (num_of_frames)
|
|
0:
|
|
begin
|
|
// prepare packet
|
|
i_length = 60;
|
|
st_data = 8'h0F;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
3:
|
|
begin
|
|
// prepare packet
|
|
i_length = 68;
|
|
st_data = 8'h01;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
6:
|
|
begin
|
|
// prepare packet
|
|
i_length = 80;
|
|
st_data = 8'hA1;
|
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
|
end
|
|
10:
|
|
begin
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// DISPLAYS
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
$display(" packet shoud be successfuly received");
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
$display(" packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun");
|
|
end
|
|
2, 4, 6: // RX FIFO overrun
|
|
begin
|
|
$display(" packet should NOT be received - RX FIFO overrun");
|
|
end
|
|
9: // RX BD overrun
|
|
begin
|
|
$display(" packet should NOT be received - RX FIFO overrun due to lack of RX BDs");
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin: set_no_resp3
|
|
if ((num_of_frames == 1) || (num_of_frames == 4)) // RX FIFO overrun!
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
if (num_of_frames == 6) // RX FIFO overrun!
|
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (eth_ma_wb_ack_i === 1'b1) // WB transfer
|
|
wait (eth_ma_wb_ack_i === 1'b0) // WB transfer
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
end
|
|
end
|
|
begin: wait_for_rec3
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
if (((data[15] !== 1) && (num_of_frames != 9)) || // RX BD must be Empty
|
|
((data[15] !== 0) && (num_of_frames == 9))) // RX BD must NOT be Empty - RX BD overrun!!!
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
while (((data[15] === 1) && (num_of_frames != 9)) ||
|
|
((data[15] === 0) && (num_of_frames == 9)))
|
|
begin
|
|
#1 check_rx_bd(num_of_bd, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
disable check_wait_for_rec3;
|
|
disable set_no_resp3;
|
|
$display(" ->packet received");
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
begin: check_wait_for_rec3
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(50) @(posedge wb_clk);
|
|
wait (wbm_working == 0);
|
|
disable wait_for_rec3;
|
|
disable set_no_resp3;
|
|
$display(" ->packet NOT received");
|
|
end
|
|
join
|
|
// PACKET checking
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (((data[15:0] !== 16'h4000) && (num_of_bd != 127)) || // without wrap bit
|
|
((data[15:0] !== 16'h6000) && (num_of_bd == 127)))
|
|
begin
|
|
`TIME;
|
|
if (num_of_bd != 127)
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 6000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
2: // RX FIFO overrun & previous packet written
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
$display(" ->previous packet written into MEM");
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
end
|
|
4, 6: // RX FIFO overrun
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'h4040)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4040", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer Error was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
end
|
|
9: // RX BD overrun
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
// NOT checked since BD value is from first packet - RX BD overrun
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_BUSY) !== `ETH_INT_BUSY)
|
|
begin
|
|
`TIME; $display("*E Interrupt BUSY was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt BUSY was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_BUSY)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except BUSY) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except BUSY) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// clear interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
num_of_frames = num_of_frames + 1;
|
|
end
|
|
// disable RX
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0;
|
|
end
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Test receive packets at one RX BD and ////
|
|
//// check addresses ( 10Mbps ). ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 14) //
|
|
begin
|
|
// TEST 14: RECEIVE PACKETS (DELAYED CRC) AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )
|
|
test_name = "TEST 14: RECEIVE PACKETS (DELAYED CRC) AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )";
|
|
`TIME; $display(" TEST 14: RECEIVE PACKETS (DELAYED CRC) AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )");
|
|
|
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// write to phy's control register for 10Mbps
|
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
|
speed = 10;
|
|
|
|
num_of_frames = 0;
|
|
i_length = 64;
|
|
while (num_of_frames < 8)
|
|
begin
|
|
// not detect carrier sense in FD and no collision
|
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
|
eth_phy.collision(0);
|
|
case (num_of_frames)
|
|
0: // unicast + PRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet (delayed CRC) is going to be received with PRO bit (wrap at 1st BD)");
|
|
end
|
|
1: // unicast
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h12;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet (delayed CRC) is going to be received without PRO bit (wrap at 1st BD)");
|
|
end
|
|
2: // wrong unicast + PRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h31;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet (delayed CRC) is going to be received with PRO bit (wrap at 1st BD)");
|
|
end
|
|
3: // wrong unicast
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet (delayed CRC) is NOT going to be received without PRO bit (wrap at 1st BD)");
|
|
end
|
|
4: // broadcast + PRO + ~BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h84;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet (delayed CRC) is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
5: // broadcast + ~BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h48;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet (delayed CRC) is going to be received without Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
6: // broadcast + PRO + BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h30;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet (delayed CRC) is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
7: // broadcast + BRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h04;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet (delayed CRC) is NOT going to be received with Reject_BRO bit (wrap at 1st BD)");
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
|
fork
|
|
begin
|
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
|
repeat(10) @(posedge mrx_clk);
|
|
end
|
|
begin: wait_for_rece0
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
#1 check_rx_bd(127, data);
|
|
if (data[15] !== 1)
|
|
begin
|
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
while (data[15] === 1)
|
|
begin
|
|
#1 check_rx_bd(127, data);
|
|
@(posedge wb_clk);
|
|
end
|
|
disable check_wait_for_rece0;
|
|
$display(" ->packet received");
|
|
repeat (1) @(posedge wb_clk);
|
|
end
|
|
begin: check_wait_for_rece0
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (MRxDV === 1'b0); // end transmit
|
|
repeat(10) @(posedge mrx_clk);
|
|
repeat(50) @(posedge wb_clk);
|
|
wait (wbm_working == 0);
|
|
disable wait_for_rece0;
|
|
$display(" ->packet NOT received");
|
|
end
|
|
join
|
|
// PACKET checking
|
|
wait (wbm_working == 0);
|
|
check_rx_bd(127, data);
|
|
case (num_of_frames)
|
|
0, 1, 4, 5:
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (data[15:0] !== 16'hC000)
|
if (data[15:0] !== 16'h6000)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (data !== 0)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
// Release packet
|
begin
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
repeat(128) @(posedge wb_clk);
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
//check_rx_bd(120, data);
|
end
|
//$display("RX BD 120 = %h", data);
|
end
|
//check_rx_bd(121, data);
|
2, 6:
|
//$display("RX BD 121 = %h", data);
|
begin
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (data[15:0] !== 16'h4040)
|
if (data[15:0] !== 16'h6080)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4040", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Receive Buffer Error was not set");
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
end
|
end
|
9: // RX BD overrun
|
3, 7:
|
begin
|
begin
|
|
|
//check_rx_bd(120, data);
|
|
//$display("RX BD 120 = %h", data);
|
|
//check_rx_bd(121, data);
|
|
//$display("RX BD 121 = %h", data);
|
|
//check_rx_bd(122, data);
|
|
//$display("RX BD 122 = %h", data);
|
|
//check_rx_bd(123, data);
|
|
//$display("RX BD 123 = %h", data);
|
|
//check_rx_bd(124, data);
|
|
//$display("RX BD 124 = %h", data);
|
|
//check_rx_bd(125, data);
|
|
//$display("RX BD 125 = %h", data);
|
|
//check_rx_bd(126, data);
|
|
//$display("RX BD 126 = %h", data);
|
|
//check_rx_bd(127, data);
|
|
//$display("RX BD 127 = %h", data);
|
|
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
// NOT checked since BD value is from first packet - RX BD overrun
|
if (data[15:0] !== 16'hE000)
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_BUSY) !== `ETH_INT_BUSY)
|
|
begin
|
begin
|
`TIME; $display("*E Interrupt BUSY was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("Interrupt BUSY was not set");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
if ((data & (~`ETH_INT_BUSY)) !== 0)
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except BUSY) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
test_fail("Other interrupts (except BUSY) were set");
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
end
|
end
|
endcase
|
endcase
|
|
// clear RX buffer descriptor
|
|
clear_rx_bd(127, 127);
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
| Line 16240... |
Line 17718... |
end
|
end
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Test receive packets at 8 RX BD with ////
|
//// Test receive packets (delayed CRC) at one RX BD and ////
|
//// RX FIFO and RX BD overrun ( 100Mbps ). ////
|
//// check addresses ( 100Mbps ). ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 13) //
|
if (test_num == 15) //
|
begin
|
begin
|
// TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )
|
// TEST 15: RECEIVE PACKETS (DELAYED CRC) AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )
|
test_name = "TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )";
|
test_name = "TEST 15: RECEIVE PACKETS (DELAYED CRC) AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )";
|
`TIME; $display(" TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )");
|
`TIME; $display(" TEST 15: RECEIVE PACKETS (DELAYED CRC) AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )");
|
// set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
|
|
wait (wbm_working == 0);
|
// set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
|
wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// unmask interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// unmask interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 100Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
|
speed = 100;
|
speed = 100;
|
|
|
// enable interrupt generation
|
|
set_rx_bd(120, 127, 1'b1, `MEMORY_BASE);
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
|
|
num_of_frames = 0;
|
num_of_frames = 0;
|
while (num_of_frames < 11)
|
i_length = 64;
|
|
while (num_of_frames < 8)
|
begin
|
begin
|
// not detect carrier sense in FD and no collision
|
// not detect carrier sense in FD and no collision
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.no_carrier_sense_rx_fd_detect(0);
|
eth_phy.collision(0);
|
eth_phy.collision(0);
|
if (num_of_frames < 2)
|
|
num_of_bd = 120 + num_of_frames;
|
|
else if (num_of_frames < 9)
|
|
num_of_bd = 120 + num_of_frames - 1;
|
|
else
|
|
num_of_bd = 120;
|
|
case (num_of_frames)
|
case (num_of_frames)
|
0:
|
0: // unicast + PRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h0F;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet (delayed CRC) is going to be received with PRO bit (wrap at 1st BD)");
|
|
end
|
|
1: // unicast + delayed CRC
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG, set delayed CRC
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h12;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Unicast packet (delayed CRC) is going to be received without PRO bit (wrap at 1st BD)");
|
|
end
|
|
2: // wrong unicast + PRO
|
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h31;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet (delayed CRC) is going to be received with PRO bit (wrap at 1st BD)");
|
|
end
|
|
3: // wrong unicast
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
// prepare packet
|
// prepare packet
|
i_length = 60;
|
|
st_data = 8'h0F;
|
st_data = 8'h0F;
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hAA02_0304_0507, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" non Unicast packet (delayed CRC) is NOT going to be received without PRO bit (wrap at 1st BD)");
|
end
|
end
|
3:
|
4: // broadcast + PRO + ~BRO
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
// prepare packet
|
// prepare packet
|
i_length = 68;
|
st_data = 8'h84;
|
st_data = 8'h01;
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
$display(" Broadcast packet (delayed CRC) is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)");
|
end
|
end
|
6:
|
5: // broadcast + ~BRO
|
begin
|
begin
|
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
// prepare packet
|
// prepare packet
|
i_length = 80;
|
st_data = 8'h48;
|
st_data = 8'hA1;
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
set_rx_packet(0, i_length, 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
append_rx_crc (0, i_length, 1'b0, 1'b0);
|
$display(" Broadcast packet (delayed CRC) is going to be received without Reject_BRO bit (wrap at 1st BD)");
|
end
|
|
10:
|
|
begin
|
|
// SET empty bit
|
|
set_rx_bd_empty(120, 127);
|
|
end
|
|
default:
|
|
begin
|
|
end
|
|
endcase
|
|
// DISPLAYS
|
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
$display(" packet shoud be successfuly received");
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
$display(" packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun");
|
|
end
|
end
|
2, 4, 6: // RX FIFO overrun
|
6: // broadcast + PRO + BRO
|
begin
|
begin
|
$display(" packet should NOT be received - RX FIFO overrun");
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_PRO | `ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h30;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet (delayed CRC) is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)");
|
end
|
end
|
9: // RX BD overrun
|
7: // broadcast + BRO
|
begin
|
begin
|
$display(" packet should NOT be received - RX FIFO overrun due to lack of RX BDs");
|
// enable interrupt generation
|
|
set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
|
|
// disable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, 32'h0,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// enable RX, set full-duplex mode, NO receive small, NO correct IFG
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
|
|
`ETH_MODER_BRO | `ETH_MODER_DLYCRCEN,
|
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// set Destination address - Byte 0 sent first
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR1, 32'h0000_AA02, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte /, /, 0, 1 of Dest. addr.
|
|
wait (wbm_working == 0);
|
|
wbm_write(`ETH_MAC_ADDR0, 32'h0304_0506, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Byte 2, 3, 4. 5 of Dest. addr.
|
|
// prepare packet
|
|
st_data = 8'h04;
|
|
set_rx_packet_delayed(0, i_length, 1'b1, 1'b0, 32'hDEAD_BEEF, 48'hFFFF_FFFF_FFFF, 48'h0708_090A_0B0C, 16'hA56A, st_data); // length without CRC
|
|
append_rx_crc_delayed(0, i_length, 1'b0, 1'b0);
|
|
$display(" Broadcast packet (delayed CRC) is NOT going to be received with Reject_BRO bit (wrap at 1st BD)");
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
end
|
end
|
endcase
|
endcase
|
|
// set wrap bit
|
|
set_rx_bd_wrap(127);
|
|
set_rx_bd_empty(127, 127);
|
fork
|
fork
|
begin
|
begin
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
#1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
end
|
end
|
begin: set_no_resp3
|
begin: wait_for_rece1
|
if ((num_of_frames == 1) || (num_of_frames == 4)) // RX FIFO overrun!
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
if (num_of_frames == 6) // RX FIFO overrun!
|
|
begin
|
|
wait (MRxDV === 1'b1); // start transmit
|
|
wait (eth_ma_wb_ack_i === 1'b1) // WB transfer
|
|
wait (eth_ma_wb_ack_i === 1'b0) // WB transfer
|
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
|
|
end
|
|
end
|
|
begin: wait_for_rec3
|
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(127, data);
|
if (((data[15] !== 1) && (num_of_frames != 9)) || // RX BD must be Empty
|
if (data[15] !== 1)
|
((data[15] !== 0) && (num_of_frames == 9))) // RX BD must NOT be Empty - RX BD overrun!!!
|
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MRxDV === 1'b0); // end transmit
|
wait (MRxDV === 1'b0); // end transmit
|
while (((data[15] === 1) && (num_of_frames != 9)) ||
|
while (data[15] === 1)
|
((data[15] === 0) && (num_of_frames == 9)))
|
|
begin
|
begin
|
#1 check_rx_bd(num_of_bd, data);
|
#1 check_rx_bd(127, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
disable check_wait_for_rec3;
|
disable check_wait_for_rece1;
|
disable set_no_resp3;
|
|
$display(" ->packet received");
|
$display(" ->packet received");
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
end
|
end
|
begin: check_wait_for_rec3
|
begin: check_wait_for_rece1
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b1); // start transmit
|
wait (MRxDV === 1'b0); // end transmit
|
wait (MRxDV === 1'b0); // end transmit
|
repeat(10) @(posedge mrx_clk);
|
repeat(10) @(posedge mrx_clk);
|
repeat(50) @(posedge wb_clk);
|
repeat(50) @(posedge wb_clk);
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
disable wait_for_rec3;
|
disable wait_for_rece1;
|
disable set_no_resp3;
|
|
$display(" ->packet NOT received");
|
$display(" ->packet NOT received");
|
end
|
end
|
join
|
join
|
// PACKET checking
|
// PACKET checking
|
case (num_of_frames)
|
|
0, 3, 5, 7, 8, 10: // correct packet received
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
|
test_fail("WB INT signal should be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (((data[15:0] !== 16'h4000) && (num_of_bd != 127)) || // without wrap bit
|
|
((data[15:0] !== 16'h6000) && (num_of_bd == 127)))
|
|
begin
|
|
`TIME;
|
|
if (num_of_bd != 127)
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
|
else
|
|
$display("*E RX buffer descriptor status is not correct: %0h instead of 6000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
|
begin
|
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Receive Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
1: // correct packet stayed in RX FIFO
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
2: // RX FIFO overrun & previous packet written
|
|
begin
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should not be set");
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
|
if (data[15:0] !== 16'hC000)
|
|
begin
|
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
|
test_fail("RX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
check_rx_bd(127, data);
|
if (data !== 0)
|
case (num_of_frames)
|
begin
|
0, 1, 4, 5:
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
begin
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
$display(" ->previous packet written into MEM");
|
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (data[15:0] !== 16'h4000)
|
if (data[15:0] !== 16'h6000)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4000", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
// check length of a PACKET
|
|
if (data[31:16] != (i_length + 4))
|
|
begin
|
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
|
fail = fail + 1;
|
|
end
|
|
// check received RX packet data and CRC
|
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of the received packet");
|
|
test_fail("Wrong data of the received packet");
|
|
fail = fail + 1;
|
|
end
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Receive Buffer Error was not set");
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
end
|
end
|
4, 6: // RX FIFO overrun
|
2, 6:
|
begin
|
begin
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b1)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should not be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should not be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
if (data[15:0] !== 16'hC000)
|
if (data[15:0] !== 16'h6080)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of C000", data[15:0]);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check interrupts
|
// check length of a PACKET
|
wait (wbm_working == 0);
|
if (data[31:16] != (i_length + 4))
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
|
begin
|
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
|
fail = fail + 1;
|
|
end
|
|
|
|
// Release packet
|
|
#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
|
repeat(128) @(posedge wb_clk);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
|
test_fail("WB INT signal should be set");
|
data[31:16], (i_length + 4));
|
|
test_fail("Wrong length of the packet out from PHY");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
// check received RX packet data and CRC
|
// check RX buffer descriptor of a packet
|
check_rx_packet(0, `MEMORY_BASE, (i_length + 4), 1'b0, 1'b0, tmp);
|
if (data[15:0] !== 16'h4040)
|
if (tmp > 0)
|
begin
|
begin
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h instead of 4040", data[15:0]);
|
`TIME; $display("*E Wrong data of the received packet");
|
test_fail("RX buffer descriptor status is not correct");
|
test_fail("Wrong data of the received packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check interrupts
|
// check interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
|
if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
|
begin
|
begin
|
`TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
|
test_fail("Interrupt Receive Buffer Error was not set");
|
test_fail("Interrupt Receive Buffer was not set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
if ((data & (~`ETH_INT_RXE)) !== 0)
|
if ((data & (~`ETH_INT_RXB)) !== 0)
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
|
test_fail("Other interrupts (except Receive Buffer Error) were set");
|
test_fail("Other interrupts (except Receive Buffer) were set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
end
|
end
|
9: // RX BD overrun
|
3, 7:
|
begin
|
begin
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b0)
|
begin
|
begin
|
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should not be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should not be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
check_rx_bd(num_of_bd, data);
|
|
// check RX buffer descriptor of a packet
|
// check RX buffer descriptor of a packet
|
// NOT checked since BD value is from first packet - RX BD overrun
|
if (data[15:0] !== 16'hE000)
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_BUSY) !== `ETH_INT_BUSY)
|
|
begin
|
begin
|
`TIME; $display("*E Interrupt BUSY was not set, interrupt reg: %0h", data);
|
`TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("Interrupt BUSY was not set");
|
test_fail("RX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
if ((data & (~`ETH_INT_BUSY)) !== 0)
|
// check interrupts
|
|
wait (wbm_working == 0);
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (data !== 0)
|
begin
|
begin
|
`TIME; $display("*E Other interrupts (except BUSY) were set, interrupt reg: %0h", data);
|
`TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
|
test_fail("Other interrupts (except BUSY) were set");
|
test_fail("Any of interrupts (except Receive Buffer) was set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
end
|
end
|
endcase
|
endcase
|
|
// clear RX buffer descriptor
|
|
clear_rx_bd(127, 127);
|
// clear interrupts
|
// clear interrupts
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b0)
|
if (wb_int !== 1'b0)
|
| Line 21621... |
Line 23096... |
eth_phy.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
|
eth_phy.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
|
delta_t = !delta_t;
|
delta_t = !delta_t;
|
end
|
end
|
endtask // set_rx_packet
|
endtask // set_rx_packet
|
|
|
|
task set_rx_packet_delayed;
|
|
input [31:0] rxpnt;
|
|
input [15:0] len;
|
|
input delayed_crc;
|
|
input plus_dribble_nibble; // if length is longer for one nibble
|
|
input [31:0] eth_data_preamble;
|
|
input [47:0] eth_dest_addr;
|
|
input [47:0] eth_source_addr;
|
|
input [15:0] eth_type_len;
|
|
input [7:0] eth_start_data;
|
|
integer i, sd, start;
|
|
reg [16:0] tmp_len;
|
|
reg [47:0] dest_addr;
|
|
reg [47:0] source_addr;
|
|
reg [15:0] type_len;
|
|
reg [21:0] buffer;
|
|
reg delta_t;
|
|
begin
|
|
buffer = rxpnt[21:0];
|
|
dest_addr = eth_dest_addr;
|
|
source_addr = eth_source_addr;
|
|
type_len = eth_type_len;
|
|
sd = eth_start_data;
|
|
delta_t = 0;
|
|
|
|
if (delayed_crc)
|
|
begin
|
|
tmp_len = len;
|
|
start = 0;
|
|
end
|
|
else
|
|
begin
|
|
tmp_len = len+4;
|
|
start = 4;
|
|
end
|
|
|
|
for(i = start; i < tmp_len; i = i + 1)
|
|
begin
|
|
if (i < 4)
|
|
begin
|
|
eth_phy.rx_mem[buffer] = eth_data_preamble[31:24];
|
|
eth_data_preamble = eth_data_preamble << 8;
|
|
end
|
|
else if (i < 10)
|
|
begin
|
|
eth_phy.rx_mem[buffer] = dest_addr[47:40];
|
|
dest_addr = dest_addr << 8;
|
|
end
|
|
else if (i < 16)
|
|
begin
|
|
eth_phy.rx_mem[buffer] = source_addr[47:40];
|
|
source_addr = source_addr << 8;
|
|
end
|
|
else if (i < 18)
|
|
begin
|
|
eth_phy.rx_mem[buffer] = type_len[15:8];
|
|
type_len = type_len << 8;
|
|
end
|
|
else
|
|
begin
|
|
eth_phy.rx_mem[buffer] = sd[7:0];
|
|
sd = sd + 1;
|
|
end
|
|
buffer = buffer + 1;
|
|
end
|
|
delta_t = !delta_t;
|
|
if (plus_dribble_nibble)
|
|
eth_phy.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
|
|
delta_t = !delta_t;
|
|
end
|
|
endtask // set_rx_packet_delayed
|
|
|
task set_rx_control_packet;
|
task set_rx_control_packet;
|
input [31:0] rxpnt;
|
input [31:0] rxpnt;
|
input [15:0] PauseTV;
|
input [15:0] PauseTV;
|
integer i;
|
integer i;
|
reg [47:0] dest_addr;
|
reg [47:0] dest_addr;
|
| Line 22046... |
Line 23593... |
end
|
end
|
delta_t = !delta_t;
|
delta_t = !delta_t;
|
end
|
end
|
endtask // check_tx_crc
|
endtask // check_tx_crc
|
|
|
|
task check_tx_crc_delayed; // used to check crc added to TX packets by MAC
|
|
input [31:0] txpnt_phy; // destination
|
|
input [15:0] len; // length in bytes without CRC
|
|
input negated_crc; // if appended CRC is correct or not
|
|
output [31:0] failure;
|
|
reg [31:0] failure;
|
|
reg [31:0] crc_calc;
|
|
reg [31:0] crc;
|
|
reg [31:0] addr_phy;
|
|
reg delta_t;
|
|
begin
|
|
addr_phy = txpnt_phy;
|
|
failure = 0;
|
|
// calculate CRC from sent packet
|
|
// serial_crc_phy_tx(addr_phy, {16'h0, len}, 1'b0, crc_calc);
|
|
//#10;
|
|
paralel_crc_phy_tx(addr_phy+4, {16'h0, len}-4, 1'b0, crc_calc);
|
|
#1;
|
|
addr_phy = addr_phy + len;
|
|
// Read CRC - BIG endian
|
|
crc[31:24] = eth_phy.tx_mem[addr_phy[21:0]];
|
|
crc[23:16] = eth_phy.tx_mem[addr_phy[21:0] + 1];
|
|
crc[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 2];
|
|
crc[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 3];
|
|
|
|
delta_t = !delta_t;
|
|
if (negated_crc)
|
|
begin
|
|
if ((~crc_calc) !== crc)
|
|
begin
|
|
`TIME;
|
|
$display("*E Negated CRC was not successfuly transmitted!");
|
|
failure = failure + 1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (crc_calc !== crc)
|
|
begin
|
|
`TIME;
|
|
$display("*E Transmitted CRC was not correct; crc_calc: %0h, crc_mem: %0h", crc_calc, crc);
|
|
failure = failure + 1;
|
|
end
|
|
end
|
|
delta_t = !delta_t;
|
|
end
|
|
endtask // check_tx_crc_delayed
|
|
|
task append_rx_crc;
|
task append_rx_crc;
|
input [31:0] rxpnt_phy; // source
|
input [31:0] rxpnt_phy; // source
|
input [15:0] len; // length in bytes without CRC
|
input [15:0] len; // length in bytes without CRC
|
input plus_dribble_nibble; // if length is longer for one nibble
|
input plus_dribble_nibble; // if length is longer for one nibble
|
input negated_crc; // if appended CRC is correct or not
|
input negated_crc; // if appended CRC is correct or not
|
| Line 22083... |
Line 23678... |
eth_phy.rx_mem[addr_phy + 3] = crc[7:0];
|
eth_phy.rx_mem[addr_phy + 3] = crc[7:0];
|
end
|
end
|
end
|
end
|
endtask // append_rx_crc
|
endtask // append_rx_crc
|
|
|
|
task append_rx_crc_delayed;
|
|
input [31:0] rxpnt_phy; // source
|
|
input [15:0] len; // length in bytes without CRC
|
|
input plus_dribble_nibble; // if length is longer for one nibble
|
|
input negated_crc; // if appended CRC is correct or not
|
|
reg [31:0] crc;
|
|
reg [7:0] tmp;
|
|
reg [31:0] addr_phy;
|
|
reg delta_t;
|
|
begin
|
|
addr_phy = rxpnt_phy + len;
|
|
delta_t = 0;
|
|
// calculate CRC from prepared packet
|
|
paralel_crc_phy_rx(rxpnt_phy+4, {16'h0, len}-4, plus_dribble_nibble, crc);
|
|
if (negated_crc)
|
|
crc = ~crc;
|
|
delta_t = !delta_t;
|
|
|
|
if (plus_dribble_nibble)
|
|
begin
|
|
tmp = eth_phy.rx_mem[addr_phy];
|
|
eth_phy.rx_mem[addr_phy] = {crc[27:24], tmp[3:0]};
|
|
eth_phy.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
|
|
eth_phy.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
|
|
eth_phy.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
|
|
eth_phy.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
|
|
end
|
|
else
|
|
begin
|
|
eth_phy.rx_mem[addr_phy] = crc[31:24];
|
|
eth_phy.rx_mem[addr_phy + 1] = crc[23:16];
|
|
eth_phy.rx_mem[addr_phy + 2] = crc[15:8];
|
|
eth_phy.rx_mem[addr_phy + 3] = crc[7:0];
|
|
end
|
|
end
|
|
endtask // append_rx_crc_delayed
|
|
|
// paralel CRC checking for PHY TX
|
// paralel CRC checking for PHY TX
|
task paralel_crc_phy_tx;
|
task paralel_crc_phy_tx;
|
input [31:0] start_addr; // start address
|
input [31:0] start_addr; // start address
|
input [31:0] len; // length of frame in Bytes without CRC length
|
input [31:0] len; // length of frame in Bytes without CRC length
|
input plus_dribble_nibble; // if length is longer for one nibble
|
input plus_dribble_nibble; // if length is longer for one nibble
|
