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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Diff between revs 318 and 331

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Line 40... Line 40...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.32  2004/03/26 15:59:21  tadejm
 
// Latest Ethernet IP core testbench.
 
//
// Revision 1.31  2003/12/05 12:46:26  tadejm
// Revision 1.31  2003/12/05 12:46:26  tadejm
// Updated testbench. Some more testcases, some repaired.
// Updated testbench. Some more testcases, some repaired.
//
//
// Revision 1.30  2003/10/17 07:45:17  markom
// Revision 1.30  2003/10/17 07:45:17  markom
// mbist signals updated according to newest convention
// mbist signals updated according to newest convention
Line 467... Line 470...
integer      tests_failed;
integer      tests_failed;
reg [799:0]  test_name; // used for tb_log_file
reg [799:0]  test_name; // used for tb_log_file
 
 
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds
reg   [3:0]  wbs_waits; // wait cycles befor WB Slave responds
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
 
 
reg          wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working
reg          wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working
 
 
 
 
Line 502... Line 505...
  $display("===========================================================================");
  $display("===========================================================================");
  $display("PHY generates ideal Carrier sense and Collision signals for following tests");
  $display("PHY generates ideal Carrier sense and Collision signals for following tests");
  $display("===========================================================================");
  $display("===========================================================================");
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
  eth_phy.carrier_sense_real_delay(0);
  eth_phy.carrier_sense_real_delay(0);
    test_mac_full_duplex_transmit(0, 21);    // 0 - 21
    test_mac_full_duplex_transmit(0, 23);    // 0 - 23
    test_mac_full_duplex_receive(0, 13);     // 0 - 13
    test_mac_full_duplex_receive(0, 15);     // 0 - 15
    test_mac_full_duplex_flow_control(0, 5); // 0 - 5
    test_mac_full_duplex_flow_control(0, 5); // 0 - 5
    test_mac_half_duplex_flow(0, 1);
    test_mac_half_duplex_flow(0, 1);
 
 
  $display("");
  $display("");
  $display("===========================================================================");
  $display("===========================================================================");
Line 660... Line 663...
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
        data = {({8{~sel[3]}}), ({8{~sel[2]}}), ({8{~sel[1]}}), ({8{~sel[0]}})};
        data = {({8{~sel[3]}}), ({8{~sel[2]}}), ({8{~sel[1]}}), ({8{~sel[0]}})};
        if (tmp_data !== data)
        if (tmp_data !== data)
        begin
        begin
          fail = fail + 1;
          fail = fail + 1;
          test_fail_num("Wrong data read out form register", i_addr);
          test_fail_num("Wrong data read out from register", i_addr);
          `TIME;
          `TIME;
          $display("Wrong data read out from register - addr %h, data %h, tmp_data %h, sel %b",
          $display("Wrong data read out from register - addr %h, data %h, tmp_data %h, sel %b",
                   addr, data, tmp_data, sel);
                   addr, data, tmp_data, sel);
        end
        end
      end
      end
Line 4340... Line 4343...
////                                                              ////
////                                                              ////
////  test_mac_full_duplex_transmit:                              ////
////  test_mac_full_duplex_transmit:                              ////
////                                                              ////
////                                                              ////
////  0: Test no transmit when all buffers are RX ( 10Mbps ).     ////
////  0: Test no transmit when all buffers are RX ( 10Mbps ).     ////
////  1: Test no transmit when all buffers are RX ( 100Mbps ).    ////
////  1: Test no transmit when all buffers are RX ( 100Mbps ).    ////
////  2: Test transmit packets form MINFL to MAXFL sizes at       ////
////  2: Test transmit packets from MINFL to MAXFL sizes at       ////
////     one TX buffer decriptor ( 10Mbps ).                      ////
////     one TX buffer decriptor ( 10Mbps ).                      ////
////  3: Test transmit packets form MINFL to MAXFL sizes at       ////
////  3: Test transmit packets from MINFL to MAXFL sizes at       ////
////     one TX buffer decriptor ( 100Mbps ).                     ////
////     one TX buffer decriptor ( 100Mbps ).                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
begin
begin
Line 4536... Line 4539...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
  ////  Test transmit packets from MINFL to MAXFL sizes at        ////
  ////  one TX buffer decriptor ( 10Mbps ).                       ////
  ////  one TX buffer decriptor ( 10Mbps ).                       ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 2) //
  if (test_num == 2) //
  begin
  begin
Line 4850... Line 4853...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
  ////  Test transmit packets from MINFL to MAXFL sizes at        ////
  ////  one TX buffer decriptor ( 100Mbps ).                      ////
  ////  one TX buffer decriptor ( 100Mbps ).                      ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 3) //
  if (test_num == 3) //
  begin
  begin
Line 5154... Line 5157...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
  ////  Test transmit packets from MINFL to MAXFL sizes at        ////
  ////  maximum TX buffer decriptors ( 10Mbps ).                  ////
  ////  maximum TX buffer decriptors ( 10Mbps ).                  ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 4) //
  if (test_num == 4) //
  begin
  begin
Line 5288... Line 5291...
        end
        end
        endcase
        endcase
        // set wrap bit
        // set wrap bit
        set_tx_bd_wrap(0);
        set_tx_bd_wrap(0);
      end
      end
      // after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
      // after first 8 number of frames, 128 frames from TX BD 0 to 127 will be transmitted
      else if ((num_of_frames - 8) == 0)
      else if ((num_of_frames - 8) == 0)
      begin
      begin
        tmp_len = i_length; // length of frame
        tmp_len = i_length; // length of frame
        tmp_bd_num = 0; // TX BD number
        tmp_bd_num = 0; // TX BD number
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
Line 5318... Line 5321...
          tmp_bd_num = tmp_bd_num + 1;
          tmp_bd_num = tmp_bd_num + 1;
        end
        end
        // set wrap bit
        // set wrap bit
        set_tx_bd_wrap(127);
        set_tx_bd_wrap(127);
      end
      end
      // after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
      // after 128 + first 8 number of frames, 19 frames from TX BD 0 to 18 will be transmitted
      else if ((num_of_frames - 8) == 20) // 128
      else if ((num_of_frames - 8) == 20) // 128
      begin
      begin
        tmp_len = tmp_len; // length of frame remaines from previous settings
        tmp_len = tmp_len; // length of frame remaines from previous settings
        tmp_bd_num = 0; // TX BD number
        tmp_bd_num = 0; // TX BD number
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
Line 5620... Line 5623...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
  ////  Test transmit packets from MINFL to MAXFL sizes at        ////
  ////  maximum TX buffer decriptors ( 100Mbps ).                 ////
  ////  maximum TX buffer decriptors ( 100Mbps ).                 ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 5) //
  if (test_num == 5) //
  begin
  begin
Line 5754... Line 5757...
        end
        end
        endcase
        endcase
        // set wrap bit
        // set wrap bit
        set_tx_bd_wrap(0);
        set_tx_bd_wrap(0);
      end
      end
      // after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
      // after first 8 number of frames, 128 frames from TX BD 0 to 127 will be transmitted
      else if ((num_of_frames - 8) == 0)
      else if ((num_of_frames - 8) == 0)
      begin
      begin
        tmp_len = i_length; // length of frame
        tmp_len = i_length; // length of frame
        tmp_bd_num = 0; // TX BD number
        tmp_bd_num = 0; // TX BD number
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
Line 5784... Line 5787...
          tmp_bd_num = tmp_bd_num + 1;
          tmp_bd_num = tmp_bd_num + 1;
        end
        end
        // set wrap bit
        // set wrap bit
        set_tx_bd_wrap(127);
        set_tx_bd_wrap(127);
      end
      end
      // after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
      // after 128 + first 8 number of frames, 19 frames from TX BD 0 to 18 will be transmitted
      else if ((num_of_frames - 8) == 20) // 128
      else if ((num_of_frames - 8) == 20) // 128
      begin
      begin
        tmp_len = tmp_len; // length of frame remaines from previous settings
        tmp_len = tmp_len; // length of frame remaines from previous settings
        tmp_bd_num = 0; // TX BD number
        tmp_bd_num = 0; // TX BD number
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
Line 6086... Line 6089...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test transmit packets form 0 to (MINFL - 1) sizes at      ////
  ////  Test transmit packets from 0 to (MINFL - 1) sizes at      ////
  ////  8 TX buffer decriptors ( 10Mbps ).                        ////
  ////  8 TX buffer decriptors ( 10Mbps ).                        ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 6) // 
  if (test_num == 6) // 
  begin
  begin
Line 6569... Line 6572...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test transmit packets form 0 to (MINFL - 1) sizes at      ////
  ////  Test transmit packets from 0 to (MINFL - 1) sizes at      ////
  ////  8 TX buffer decriptors ( 100Mbps ).                       ////
  ////  8 TX buffer decriptors ( 100Mbps ).                       ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 7) // 
  if (test_num == 7) // 
  begin
  begin
Line 7631... Line 7634...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test transmit packets (no pads) form 0 to (MINFL - 1)     ////
  ////  Test transmit packets (no pads) from 0 to (MINFL - 1)     ////
  ////  sizes at 8 TX buffer decriptors ( 100Mbps ).              ////
  ////  sizes at 8 TX buffer decriptors ( 100Mbps ).              ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 9) // 
  if (test_num == 9) // 
  begin
  begin
Line 11209... Line 11212...
      test_ok;
      test_ok;
    else
    else
      fail = 0;
      fail = 0;
  end
  end
 
 
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
 
 
 
end
 
endtask // test_mac_full_duplex_transmit
 
 
 
 
 
task test_mac_full_duplex_receive;
 
  input  [31:0]  start_task;
 
  input  [31:0]  end_task;
 
  integer        bit_start_1;
 
  integer        bit_end_1;
 
  integer        bit_start_2;
 
  integer        bit_end_2;
 
  integer        num_of_reg;
 
  integer        num_of_frames;
 
  integer        num_of_bd;
 
  integer        i_addr;
 
  integer        i_data;
 
  integer        i_length;
 
  integer        tmp_len;
 
  integer        tmp_bd;
 
  integer        tmp_bd_num;
 
  integer        tmp_data;
 
  integer        tmp_ipgt;
 
  integer        test_num;
 
  reg    [31:0]  tx_bd_num;
 
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
 
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
 
  integer        i;
 
  integer        i1;
 
  integer        i2;
 
  integer        i3;
 
  integer        fail;
 
  integer        speed;
 
  reg            frame_started;
 
  reg            frame_ended;
 
  reg            wait_for_frame;
 
  reg            check_frame;
 
  reg            stop_checking_frame;
 
  reg            first_fr_received;
 
  reg    [31:0]  addr;
 
  reg    [31:0]  data;
 
  reg    [31:0]  tmp;
 
  reg    [ 7:0]  st_data;
 
  reg    [15:0]  max_tmp;
 
  reg    [15:0]  min_tmp;
 
begin
 
// MAC FULL DUPLEX RECEIVE TEST
 
test_heading("MAC FULL DUPLEX RECEIVE TEST");
 
$display(" ");
 
$display("MAC FULL DUPLEX RECEIVE TEST");
 
fail = 0;
 
 
 
// reset MAC registers
 
hard_reset;
 
// set wb slave response
 
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
 
 
 
  /*
 
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
 
  -------------------------------------------------------------------------------------
 
  set_tx_bd
 
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
 
  set_tx_bd_wrap
 
    (tx_bd_num_end[6:0]);
 
  set_tx_bd_ready
 
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
 
  check_tx_bd
 
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
 
  clear_tx_bd
 
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
 
 
 
  TASKS for set and control RX buffer descriptors:
 
  ------------------------------------------------
 
  set_rx_bd
 
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
 
  set_rx_bd_wrap
 
    (rx_bd_num_end[6:0]);
 
  set_rx_bd_empty
 
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
 
  check_rx_bd
 
    (rx_bd_num_end[6:0], rx_bd_status);
 
  clear_rx_bd
 
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
 
 
 
  TASKS for set and check TX packets:
 
  -----------------------------------
 
  set_tx_packet
 
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
 
  check_tx_packet
 
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
 
 
 
  TASKS for set and check RX packets:
 
  -----------------------------------
 
  set_rx_packet
 
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
 
  check_rx_packet
 
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
 
 
 
  TASKS for append and check CRC to/of TX packet:
 
  -----------------------------------------------
 
  append_tx_crc
 
    (txpnt_wb[31:0], len[15:0], negated_crc);
 
  check_tx_crc
 
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
 
 
 
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
 
  --------------------------------------------------------------------------------
 
  append_rx_crc
 
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
 
  */
 
 
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  test_mac_full_duplex_receive:                               ////
 
////                                                              ////
 
////  0: Test no receive when all buffers are TX ( 10Mbps ).      ////
 
////  1: Test no receive when all buffers are TX ( 100Mbps ).     ////
 
////  2: Test receive packet synchronization with receive         ////
 
////     disable/enable ( 10Mbps ).                               ////
 
////  3: Test receive packet synchronization with receive         ////
 
////     disable/enable ( 100Mbps ).                              ////
 
////  4: Test receive packets form MINFL to MAXFL sizes at        ////
 
////     one RX buffer decriptor ( 10Mbps ).                      ////
 
////  5: Test receive packets form MINFL to MAXFL sizes at        ////
 
////     one RX buffer decriptor ( 100Mbps ).                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
 
begin
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test no receive when all buffers are TX ( 10Mbps ).       ////
  ////  Test transmit packets (delayed CRC) from MINFL to MAXFL   ////
 
  ////  sizes at one TX buffer decriptor ( 10Mbps ).              ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 0) //
  if (test_num == 22) //
  begin
  begin
    // TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
    // TEST 22: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
    test_name   = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
    test_name = "TEST 22: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
    `TIME; $display("  TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
    `TIME; $display("  TEST 22: TRANSMIT (DELAYED CRC) PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
 
 
    // unmask interrupts
    max_tmp = 0;
    wait (wbm_working == 0);
    min_tmp = 0;
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
    // set one TX buffer descriptor - must be set before TX enable
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // set all buffer descriptors to TX - must be set before RX enable
 
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // enable RX, set full-duplex mode, receive small, NO correct IFG
    // enable TX, set full-duplex mode, NO padding and CRC appending
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // prepare two packets of MAXFL length
 
    wait (wbm_working == 0);
 
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
 
    min_tmp = tmp[31:16];
 
    st_data = 8'h01;
 
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
 
    st_data = 8'h10;
 
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
 
    // check WB INT signal
 
    if (wb_int !== 1'b0)
 
    begin
 
      test_fail("WB INT signal should not be set");
 
      fail = fail + 1;
 
    end
 
 
    // write to phy's control register for 10Mbps
    // write to phy's control register for 10Mbps
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    speed = 10;
    speed = 10;
 
 
    i = 0;
    i_length = (min_tmp - 4);
    while (i < 128)
    while (i_length <= (max_tmp - 4))
    begin
    begin
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
      // choose generating carrier sense and collision for first and last 64 lengths of frames
 
      case (i_length[1:0])
 
      2'h0: // Interrupt is generated
      begin
      begin
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
        // enable interrupt generation
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
        // unmask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1,
 
                                 wbm_init_waits, wbm_subseq_waits);
 
        // not detect carrier sense in FD and no collision
 
        eth_phy.carrier_sense_tx_fd_detect(0);
 
        eth_phy.collision(0);
      end
      end
      set_rx_bd_wrap(i);
      2'h1: // Interrupt is not generated
      set_rx_bd_empty(0, i);
 
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
 
      begin
      begin
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
        // enable interrupt generation
        repeat(10) @(posedge mrx_clk);
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
 
        // mask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
        // detect carrier sense in FD and no collision
 
        eth_phy.carrier_sense_tx_fd_detect(1);
 
        eth_phy.collision(0);
      end
      end
      @(posedge mrx_clk);
      2'h2: // Interrupt is not generated
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
 
      begin
 
        check_rx_bd(0, tmp);
 
        #1;
 
        if (tmp[15] === 1'b0)
 
        begin
        begin
          test_fail("Receive should not start at all");
        // disable interrupt generation
          fail = fail + 1;
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
        // unmask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
        // not detect carrier sense in FD and set collision
 
        eth_phy.carrier_sense_tx_fd_detect(0);
 
        eth_phy.collision(1);
        end
        end
        if (tmp[7:0] !== 0)
      default: // 2'h3: // Interrupt is not generated
        begin
        begin
          test_fail("Receive should not be finished since it should not start at all");
        // disable interrupt generation
          fail = fail + 1;
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
        // mask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
        // detect carrier sense in FD and set collision
 
        eth_phy.carrier_sense_tx_fd_detect(1);
 
        eth_phy.collision(1);
        end
        end
 
      endcase
 
      eth_phy.set_tx_mem_addr(max_tmp);
 
      // set wrap bit
 
      set_tx_bd_wrap(0);
 
      set_tx_bd_ready(0, 0);
 
      #1 check_tx_bd(0, data);
 
 
 
 
 
      if (i_length < min_tmp) // just first four
 
      begin
 
        while (data[15] === 1)
 
        begin
 
          #1 check_tx_bd(0, data);
        @(posedge wb_clk);
        @(posedge wb_clk);
      end
      end
      wait (wbm_working == 0);
        repeat (1) @(posedge wb_clk);
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
      if (tmp[6:0] !== 0)
 
      begin
 
        test_fail("Receive should not get INT since it should not start at all");
 
        fail = fail + 1;
 
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
 
      end
      end
      clear_rx_bd(0, i);
      else if (i_length > (max_tmp - 8)) // just last four
      if ((i < 5) || (i > 124))
      begin
        i = i + 1;
        tmp = 0;
      else
        wait (MTxEn === 1'b1); // start transmit
        i = i + 120;
        while (tmp < (i_length - 20))
 
        begin
 
          #1 tmp = tmp + 1;
 
          @(posedge wb_clk);
 
        end
 
        #1 check_tx_bd(0, data);
 
        while (data[15] === 1)
 
        begin
 
          #1 check_tx_bd(0, data);
 
          @(posedge wb_clk);
 
        end
 
        repeat (1) @(posedge wb_clk);
    end
    end
    // disable RX
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
 
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    if(fail == 0)
 
      test_ok;
 
    else
    else
      fail = 0;
      begin
 
        wait (MTxEn === 1'b1); // start transmit
 
        #1 check_tx_bd(0, data);
 
        if (data[15] !== 1)
 
        begin
 
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
 
          fail = fail + 1;
  end
  end
 
        wait (MTxEn === 1'b0); // end transmit
 
        while (data[15] === 1)
  ////////////////////////////////////////////////////////////////////
 
  ////                                                            ////
 
  ////  Test no receive when all buffers are TX ( 100Mbps ).      ////
 
  ////                                                            ////
 
  ////////////////////////////////////////////////////////////////////
 
  if (test_num == 1) //
 
  begin
  begin
    // TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
          #1 check_tx_bd(0, data);
    test_name   = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
          @(posedge wb_clk);
    `TIME; $display("  TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
        end
 
        repeat (1) @(posedge wb_clk);
 
      end
 
 
    // unmask interrupts
      repeat(5) @(posedge mtx_clk);  // Wait some time so PHY stores the CRC
    wait (wbm_working == 0);
 
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // set all buffer descriptors to TX - must be set before RX enable
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // enable RX, set full-duplex mode, receive small, NO correct IFG
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
 
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
 
 
    // write to phy's control register for 100Mbps
      // check length of a PACKET
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
      if (eth_phy.tx_len != (i_length + 4))
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
      begin
    speed = 100;
        test_fail("Wrong length of the packet out from MAC");
 
        fail = fail + 1;
 
      end
 
      // checking in the following if statement is performed only for first and last 64 lengths
 
      if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
 
      begin
 
        // check transmitted TX packet data
 
        if (i_length[0] == 0)
 
        begin
 
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
 
        end
 
        else
 
        begin
 
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
 
        end
 
        if (tmp > 0)
 
        begin
 
          test_fail("Wrong data of the transmitted packet");
 
          fail = fail + 1;
 
        end
 
        // check transmited TX packet CRC
 
        check_tx_crc_delayed(max_tmp, i_length, 1'b0, tmp); // length without CRC
 
 
    i = 0;
        if (tmp > 0)
    while (i < 128)
 
    begin
    begin
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
          test_fail("Wrong CRC of the transmitted packet");
 
          fail = fail + 1;
 
        end
 
      end
 
      // check WB INT signal
 
      if (i_length[1:0] == 2'h0)
      begin
      begin
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
        if (wb_int !== 1'b1)
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
        begin
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
          `TIME; $display("*E WB INT signal should be set");
 
          test_fail("WB INT signal should be set");
 
          fail = fail + 1;
      end
      end
      set_rx_bd_wrap(i);
      end
      set_rx_bd_empty(0, i);
      else
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
 
      begin
      begin
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
        if (wb_int !== 1'b0)
        repeat(10) @(posedge mrx_clk);
        begin
 
          `TIME; $display("*E WB INT signal should not be set");
 
          test_fail("WB INT signal should not be set");
 
          fail = fail + 1;
      end
      end
      @(posedge mrx_clk);
      end
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
      // check TX buffer descriptor of a packet
 
      check_tx_bd(0, data);
 
      if (i_length[1] == 1'b0) // interrupt enabled
      begin
      begin
        check_rx_bd(0, tmp);
        if (data[15:0] !== 16'h7800)
        #1;
 
        if (tmp[15] === 1'b0)
 
        begin
        begin
          test_fail("Receive should not start at all");
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
 
          test_fail("TX buffer descriptor status is not correct");
          fail = fail + 1;
          fail = fail + 1;
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
 
        end
        end
        if (tmp[7:0] !== 0)
      end
 
      else // interrupt not enabled
        begin
        begin
          test_fail("Receive should not be finished since it should not start at all");
        if (data[15:0] !== 16'h3800)
 
        begin
 
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
 
          test_fail("TX buffer descriptor status is not correct");
          fail = fail + 1;
          fail = fail + 1;
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
 
        end
        end
        @(posedge wb_clk);
 
      end
      end
 
      // clear TX buffer descriptor
 
      clear_tx_bd(0, 0);
 
      // check interrupts
      wait (wbm_working == 0);
      wait (wbm_working == 0);
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      if (tmp[6:0] !== 0)
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
      begin
      begin
        test_fail("Receive should not get INT since it should not start at all");
        if ((data & `ETH_INT_TXB) !== 1'b1)
 
        begin
 
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
 
          test_fail("Interrupt Transmit Buffer was not set");
        fail = fail + 1;
        fail = fail + 1;
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
 
      end
      end
      clear_rx_bd(0, i);
        if ((data & (~`ETH_INT_TXB)) !== 0)
      if ((i < 5) || (i > 124))
        begin
        i = i + 1;
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
 
          test_fail("Other interrupts (except Transmit Buffer) were set");
 
          fail = fail + 1;
 
        end
 
      end
      else
      else
        i = i + 120;
      begin
 
        if (data !== 0)
 
        begin
 
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
 
          test_fail("Any of interrupts (except Transmit Buffer) was set");
 
          fail = fail + 1;
    end
    end
    // disable RX
      end
 
      // clear interrupts
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              `ETH_MODER_PRO | `ETH_MODER_BRO,
      // check WB INT signal
 
      if (wb_int !== 1'b0)
 
      begin
 
        test_fail("WB INT signal should not be set");
 
        fail = fail + 1;
 
      end
 
      // INTERMEDIATE DISPLAYS
 
      if ((i_length + 4) == (min_tmp + 64))
 
      begin
 
        // starting length is min_tmp, ending length is (min_tmp + 64)
 
        $display("    pads appending to packets is NOT selected");
 
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
 
                 min_tmp, (min_tmp + 64));
 
        // set padding, remain the rest
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
 
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
      end
 
      else if ((i_length + 4) == (max_tmp - 16))
 
      begin
 
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
 
        $display("    pads appending to packets is selected");
 
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
 
                 (min_tmp + 64 + 128), tmp_data);
 
        // reset padding, remain the rest
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
 
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
      end
 
      else if ((i_length + 4) == max_tmp)
 
      begin
 
        $display("    pads appending to packets is NOT selected");
 
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
 
                 (max_tmp - (4 + 16)), max_tmp);
 
      end
 
      // set length (loop variable)
 
      if ((i_length + 4) < (min_tmp + 64))
 
        i_length = i_length + 1;
 
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
 
      begin
 
        i_length = i_length + 128;
 
        tmp_data = i_length + 4; // last tmp_data is ending length
 
      end
 
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
 
        i_length = max_tmp - (4 + 16);
 
      else if ((i_length + 4) >= (max_tmp - 16))
 
        i_length = i_length + 1;
 
      else
 
      begin
 
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
 
        #10 $stop;
 
      end
 
    end
 
    // disable TX
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    if(fail == 0)
    if(fail == 0)
      test_ok;
      test_ok;
    else
    else
      fail = 0;
      fail = 0;
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test receive packet synchronization with receive          ////
  ////  Test transmit packets (DELAYED CRC) from MINFL to MAXFL   ////
  ////  disable/enable ( 10Mbps ).                                ////
  ////  sizes at one TX buffer decriptor ( 100Mbps ).             ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 2) //
  if (test_num == 23) //
  begin
  begin
    // TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
    // TEST 23: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
    test_name   = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
    test_name = "TEST 23: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
    `TIME; $display("  TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
    `TIME; $display("  TEST 23: TRANSMIT PACKETS (DELAYED CRC) FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
 
 
    // unmask interrupts
    max_tmp = 0;
    wait (wbm_working == 0);
    min_tmp = 0;
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
    // set one TX buffer descriptor - must be set before TX enable
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
 
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
    // enable TX, set full-duplex mode, NO padding and CRC appending
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // prepare two packets of MAXFL length
    // prepare two packets of MAXFL length
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    min_tmp = tmp[31:16];
    min_tmp = tmp[31:16];
    st_data = 8'h0F;
    st_data = 8'h5A;
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
    st_data = 8'h10;
    st_data = 8'h1A;
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
 
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
 
    // check WB INT signal
    // check WB INT signal
    if (wb_int !== 1'b0)
    if (wb_int !== 1'b0)
    begin
    begin
      test_fail("WB INT signal should not be set");
      test_fail("WB INT signal should not be set");
      fail = fail + 1;
      fail = fail + 1;
    end
    end
 
 
    // write to phy's control register for 10Mbps
    // write to phy's control register for 100Mbps
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    speed = 10;
    speed = 100;
 
 
    frame_started = 0;
 
    frame_ended = 0;
 
    wait_for_frame = 0;
 
    check_frame = 0;
 
    stop_checking_frame = 0;
 
    first_fr_received = 1; // at the beginning the first frame of each two will be received!
 
 
 
    num_of_frames = 0; // 
    i_length = (min_tmp - 4);
    num_of_bd = 0;
    while (i_length <= (max_tmp - 4))
    i_length = (min_tmp + 1); // 5 bytes longer than MINFL
 
    while (i_length < (max_tmp - 4))
 
    begin
    begin
      // choose generating carrier sense and collision 
      // choose generating carrier sense and collision 
      case (num_of_frames[1:0])
      case (i_length[1:0])
      2'h0: // Interrupt is generated
      2'h0: // Interrupt is generated
      begin
      begin
        // enable interrupt generation
        // enable interrupt generation
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
 
        // unmask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
        // not detect carrier sense in FD and no collision
        // not detect carrier sense in FD and no collision
        eth_phy.no_carrier_sense_rx_fd_detect(0);
        eth_phy.carrier_sense_tx_fd_detect(0);
        eth_phy.collision(0);
        eth_phy.collision(0);
      end
      end
      2'h1: // Interrupt is generated
      2'h1: // Interrupt is not generated
      begin
      begin
        // enable interrupt generation
        // enable interrupt generation
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
 
        // mask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
        // detect carrier sense in FD and no collision
        // detect carrier sense in FD and no collision
        eth_phy.no_carrier_sense_rx_fd_detect(1);
        eth_phy.carrier_sense_tx_fd_detect(1);
        eth_phy.collision(0);
        eth_phy.collision(0);
      end
      end
      2'h2: // Interrupt is generated
      2'h2: // Interrupt is not generated
      begin
      begin
        // disable interrupt generation
        // disable interrupt generation
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
 
        // unmask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
        // not detect carrier sense in FD and set collision
        // not detect carrier sense in FD and set collision
        eth_phy.no_carrier_sense_rx_fd_detect(0);
        eth_phy.carrier_sense_tx_fd_detect(0);
        eth_phy.collision(1);
        eth_phy.collision(1);
      end
      end
      default: // 2'h3: // Interrupt is generated
      default: // 2'h3: // Interrupt is not generated
      begin
      begin
        // disable interrupt generation
        // disable interrupt generation
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
 
        // mask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
        // detect carrier sense in FD and set collision
        // detect carrier sense in FD and set collision
        eth_phy.no_carrier_sense_rx_fd_detect(1);
        eth_phy.carrier_sense_tx_fd_detect(1);
        eth_phy.collision(1);
        eth_phy.collision(1);
      end
      end
      endcase
      endcase
 
      eth_phy.set_tx_mem_addr(max_tmp);
      // set wrap bit
      // set wrap bit
      set_rx_bd_wrap(118);
      set_tx_bd_wrap(0);
      set_rx_bd_empty(118, 118);
      set_tx_bd_ready(0, 0);
      check_frame = 0;
      #1 check_tx_bd(0, data);
      stop_checking_frame = 0;
      if (i_length < min_tmp) // just first four
      tmp_data = 0;
 
      fork
 
        begin // enable RX MAC on first of each two packets - every second should be recived normaly
 
          if (num_of_frames[0] == 1'b0)
 
          begin
 
            repeat(1) @(posedge wb_clk);
 
            if (num_of_frames[1] == 1'b0)
 
            begin
 
              repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
 
            end
 
            else
 
            begin
 
              @(posedge mrx_clk);
 
              repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
 
            end
 
            // enable RX, set full-duplex mode, NO receive small, NO correct IFG
 
            wbm_init_waits = 4'h0;
 
            wbm_subseq_waits = 4'h0;
 
            #1 wait (wbm_working == 0);
 
            wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
 
                      `ETH_MODER_PRO | `ETH_MODER_BRO,
 
                      4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
 
          end
 
        end
 
        begin // send a packet from PHY RX
 
          repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
 
          if (num_of_frames[1] == 1'b0)
 
          begin
 
            set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
 
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
 
          end
 
          else
 
          begin
 
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
 
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
 
          end
 
        end
 
        begin: send_packet0
 
          wait (MRxDV === 1'b1); // start transmit
 
          wait (MRxDV === 1'b0); // end transmit
 
          check_frame = 1;
 
          repeat(10) @(posedge mrx_clk);
 
          repeat(15) @(posedge wb_clk);
 
          stop_checking_frame = 1;
 
        end
 
        begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
 
          @(posedge eth_sl_wb_ack_o or posedge MRxDV);
 
          if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
 
          begin
 
            tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
 
          end
 
          else if (MRxDV === 1'b1)
 
          begin
          begin
            while (eth_sl_wb_ack_o === 1'b0)
        while (data[15] === 1)
            begin
            begin
 
          #1 check_tx_bd(0, data);
              @(posedge wb_clk);
              @(posedge wb_clk);
              tmp_data = tmp_data + 1;
 
            end
            end
            tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
        repeat (1) @(posedge wb_clk);
          end
          end
          else if (eth_sl_wb_ack_o === 1'b1)
      else if (i_length > (max_tmp - 8)) // just last four
          begin
          begin
            @(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
        tmp = 0;
            while (MRxDV === 1'b0)
        wait (MTxEn === 1'b1); // start transmit
 
        while (tmp < (i_length - 20))
            begin
            begin
 
          #1 tmp = tmp + 1;
              @(posedge wb_clk);
              @(posedge wb_clk);
              tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
 
            end
 
          end
          end
        end
        #1 check_tx_bd(0, data);
        begin // check packet
        while (data[15] === 1)
          wait (check_frame == 1);
 
          check_rx_bd(118, tmp_bd);
 
          while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
 
          begin
          begin
            #1 check_rx_bd(118, tmp_bd);
          #1 check_tx_bd(0, data);
            @(posedge wb_clk);
            @(posedge wb_clk);
          end
          end
          if (num_of_frames[0] == 1'b0)
        repeat (1) @(posedge wb_clk);
          begin
 
            if (tmp_bd[15] === 1)
 
            begin
 
              if (first_fr_received == 1)
 
              begin
 
                first_fr_received = 0;
 
                $display("    %0d packets (without this one) are checked - packets are received by two in a set",
 
                         num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
 
                $display("    From this moment:");
 
                $display("    first one of two packets (including this one) is not accepted due to late RX enable");
 
                if (tmp_data[31])
 
                  $display("    ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
 
                else
 
                  $display("    ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
 
              end
              end
              // check FB, etc.
      else
              if (tmp_bd[31:0] !== 32'h0000_E000)
 
              begin
              begin
                `TIME; $display("*E RX buffer descriptor status of NOT received packet is not correct: %0h", tmp_bd[31:0]);
        wait (MTxEn === 1'b1); // start transmit
                test_fail("RX buffer descriptor status of NOT received packet is not correct");
        #1 check_tx_bd(0, data);
                fail = fail + 1;
        if (data[15] !== 1)
              end
 
            end
 
            // else // (tmp_bd[15] === 0) - check FB, packet, etc.
 
          end
 
          else // (num_of_frames[0] == 1'b1)
 
          begin
          begin
            if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
            begin // check NOTHING
 
                `TIME; $display("*E RX packet should be accepted, buffer descriptor is not correct: %0h", tmp_bd[31:0]);
 
                test_fail("RX packet should be accepted, buffer descriptor is not correct");
 
                fail = fail + 1;
                fail = fail + 1;
            end
            end
            // else // (tmp_bd[15] === 0) - check FB, packet, etc.
        wait (MTxEn === 1'b0); // end transmit
 
        while (data[15] === 1)
 
        begin
 
          #1 check_tx_bd(0, data);
 
          @(posedge wb_clk);
          end
          end
          if (stop_checking_frame == 0)
        repeat (1) @(posedge wb_clk);
            disable send_packet1;
 
        end
        end
      join
 
      // ONLY IF packet was received!
 
      if (tmp_bd[15] === 0)
 
      begin
 
        // check length of a PACKET
        // check length of a PACKET
        if (tmp_bd[31:16] != (i_length + 4))
      if (eth_phy.tx_len != (i_length + 4))
        begin
        begin
          `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
        test_fail("Wrong length of the packet out from MAC");
                          tmp_bd[31:16], (i_length + 4));
 
          test_fail("Wrong length of the packet out from PHY");
 
          fail = fail + 1;
          fail = fail + 1;
        end
        end
        // check received RX packet data and CRC
      // check transmitted TX packet data
        if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
      if (i_length[0] == 0)
        begin
 
          if (num_of_frames[1] == 1'b0)
 
          begin
          begin
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
        check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
          end
          end
          else
          else
          begin
          begin
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
        check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
          end
          end
          if (tmp > 0)
          if (tmp > 0)
          begin
          begin
            `TIME; $display("*E Wrong data of the received packet");
        test_fail("Wrong data of the transmitted packet");
            test_fail("Wrong data of the received packet");
 
            fail = fail + 1;
            fail = fail + 1;
          end
          end
        end
      // check transmited TX packet CRC
        else // if PREVIOUS RX buffer descriptor was ready
      check_tx_crc_delayed(max_tmp, i_length, 1'b0, tmp); // length without CRC
        begin
      if (tmp > 0)
          if (num_of_frames[1] == 1'b0)
 
          begin
          begin
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
        test_fail("Wrong CRC of the transmitted packet");
 
        fail = fail + 1;
          end
          end
          else
      // check WB INT signal
 
      if (i_length[1:0] == 2'h0)
          begin
          begin
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
        if (wb_int !== 1'b1)
          end
 
          if (tmp > 0)
 
          begin
          begin
            `TIME; $display("*E Wrong data of the received packet");
          `TIME; $display("*E WB INT signal should be set");
            test_fail("Wrong data of the received packet");
          test_fail("WB INT signal should be set");
            fail = fail + 1;
            fail = fail + 1;
          end
          end
        end
        end
      end
      else
      // check WB INT signal
 
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
 
      begin
      begin
        if (wb_int !== 1'b0)
        if (wb_int !== 1'b0)
        begin
        begin
          `TIME; $display("*E WB INT signal should not be set");
          `TIME; $display("*E WB INT signal should not be set");
          test_fail("WB INT signal should not be set");
          test_fail("WB INT signal should not be set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      else
      // check TX buffer descriptor of a packet
 
      check_tx_bd(0, data);
 
      if (i_length[1] == 1'b0) // interrupt enabled
      begin
      begin
        if (wb_int !== 1'b1)
        if (data[15:0] !== 16'h7800)
        begin
        begin
          `TIME; $display("*E WB INT signal should be set");
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
          test_fail("WB INT signal should be set");
          test_fail("TX buffer descriptor status is not correct");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      // check RX buffer descriptor of a packet - only 15 LSBits
      else // interrupt not enabled
      check_rx_bd(118, data);
 
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
 
      begin
      begin
        if (data[15:0] !== 16'hE000)
        if (data[15:0] !== 16'h3800)
        begin
 
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
 
          test_fail("RX buffer descriptor status is not correct");
 
          fail = fail + 1;
 
        end
 
      end
 
      else // interrupt enabled
 
      begin
 
        if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
 
        begin
        begin
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
          test_fail("RX buffer descriptor status is not correct");
          test_fail("TX buffer descriptor status is not correct");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
 
      // clear TX buffer descriptor
 
      clear_tx_bd(0, 0);
      // check interrupts
      // check interrupts
      wait (wbm_working == 0);
      wait (wbm_working == 0);
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
      begin
      begin
        if (data !== 0)
        if ((data & `ETH_INT_TXB) !== 1'b1)
        begin
        begin
          `TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
          test_fail("Any of interrupts was set");
          test_fail("Interrupt Transmit Buffer was not set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
        if ((data & (~`ETH_INT_TXB)) !== 0)
      else
 
      begin
 
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
 
        begin
        begin
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
          test_fail("Interrupt Receive Buffer was not set");
          test_fail("Other interrupts (except Transmit Buffer) were set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
        if ((data & (~`ETH_INT_RXB)) !== 0)
      end
 
      else
        begin
        begin
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
        if (data !== 0)
          test_fail("Other interrupts (except Receive Buffer) were set");
        begin
 
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h", data);
 
          test_fail("Any of interrupts (except Transmit Buffer) was set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      // clear interrupts
      // clear interrupts
      wait (wbm_working == 0);
      wait (wbm_working == 0);
Line 11859... Line 11774...
      if (wb_int !== 1'b0)
      if (wb_int !== 1'b0)
      begin
      begin
        test_fail("WB INT signal should not be set");
        test_fail("WB INT signal should not be set");
        fail = fail + 1;
        fail = fail + 1;
      end
      end
      // disable RX after two packets
      // INTERMEDIATE DISPLAYS
      if (num_of_frames[0] == 1'b1)
      if ((i_length + 4) == (min_tmp + 64))
      begin
      begin
        // disable RX, set full-duplex mode, NO receive small, NO correct IFG
        // starting length is min_tmp, ending length is (min_tmp + 64)
 
        $display("    pads appending to packets is NOT selected");
 
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
 
                 min_tmp, (min_tmp + 64));
 
        // set padding, remain the rest
        wait (wbm_working == 0);
        wait (wbm_working == 0);
        wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
                  4'hF, 1, 4'h0, 4'h0); // write ASAP
 
      end
      end
      // the number of frame transmitted
      else if ((i_length + 4) == (max_tmp - 16))
      num_of_frames = num_of_frames + 1;
      begin
      num_of_bd = 0;
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
      // set length (LOOP variable)
        $display("    pads appending to packets is selected");
      if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
        i_length = (max_tmp - 4);
                 (min_tmp + 64 + 128), tmp_data);
      @(posedge wb_clk);
        // reset padding, remain the rest
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
 
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    end
    end
    // disable RX
      else if ((i_length + 4) == max_tmp)
 
      begin
 
        $display("    pads appending to packets is NOT selected");
 
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
 
                 (max_tmp - (4 + 16)), max_tmp);
 
      end
 
      // set length (loop variable)
 
      if ((i_length + 4) < (min_tmp + 64))
 
        i_length = i_length + 1;
 
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
 
      begin
 
        i_length = i_length + 128;
 
        tmp_data = i_length + 4; // last tmp_data is ending length
 
      end
 
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
 
        i_length = max_tmp - (4 + 16);
 
      else if ((i_length + 4) >= (max_tmp - 16))
 
        i_length = i_length + 1;
 
      else
 
      begin
 
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
 
        #10 $stop;
 
      end
 
    end
 
    // disable TX
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN | `ETH_MODER_DLYCRCEN,
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    if(fail == 0)
    if(fail == 0)
      test_ok;
      test_ok;
    else
    else
      fail = 0;
      fail = 0;
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
 
 
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
 
 
 
end
 
endtask // test_mac_full_duplex_transmit
 
 
 
 
 
task test_mac_full_duplex_receive;
 
  input  [31:0]  start_task;
 
  input  [31:0]  end_task;
 
  integer        bit_start_1;
 
  integer        bit_end_1;
 
  integer        bit_start_2;
 
  integer        bit_end_2;
 
  integer        num_of_reg;
 
  integer        num_of_frames;
 
  integer        num_of_bd;
 
  integer        i_addr;
 
  integer        i_data;
 
  integer        i_length;
 
  integer        tmp_len;
 
  integer        tmp_bd;
 
  integer        tmp_bd_num;
 
  integer        tmp_data;
 
  integer        tmp_ipgt;
 
  integer        test_num;
 
  reg    [31:0]  tx_bd_num;
 
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
 
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
 
  integer        i;
 
  integer        i1;
 
  integer        i2;
 
  integer        i3;
 
  integer        fail;
 
  integer        speed;
 
  reg            frame_started;
 
  reg            frame_ended;
 
  reg            wait_for_frame;
 
  reg            check_frame;
 
  reg            stop_checking_frame;
 
  reg            first_fr_received;
 
  reg    [31:0]  addr;
 
  reg    [31:0]  data;
 
  reg    [31:0]  tmp;
 
  reg    [ 7:0]  st_data;
 
  reg    [15:0]  max_tmp;
 
  reg    [15:0]  min_tmp;
 
begin
 
// MAC FULL DUPLEX RECEIVE TEST
 
test_heading("MAC FULL DUPLEX RECEIVE TEST");
 
$display(" ");
 
$display("MAC FULL DUPLEX RECEIVE TEST");
 
fail = 0;
 
 
 
// reset MAC registers
 
hard_reset;
 
// set wb slave response
 
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
 
 
 
  /*
 
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
 
  -------------------------------------------------------------------------------------
 
  set_tx_bd
 
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
 
  set_tx_bd_wrap
 
    (tx_bd_num_end[6:0]);
 
  set_tx_bd_ready
 
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
 
  check_tx_bd
 
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
 
  clear_tx_bd
 
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
 
 
 
  TASKS for set and control RX buffer descriptors:
 
  ------------------------------------------------
 
  set_rx_bd
 
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
 
  set_rx_bd_wrap
 
    (rx_bd_num_end[6:0]);
 
  set_rx_bd_empty
 
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
 
  check_rx_bd
 
    (rx_bd_num_end[6:0], rx_bd_status);
 
  clear_rx_bd
 
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
 
 
 
  TASKS for set and check TX packets:
 
  -----------------------------------
 
  set_tx_packet
 
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
 
  check_tx_packet
 
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
 
 
 
  TASKS for set and check RX packets:
 
  -----------------------------------
 
  set_rx_packet
 
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
 
  check_rx_packet
 
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
 
 
 
  TASKS for append and check CRC to/of TX packet:
 
  -----------------------------------------------
 
  append_tx_crc
 
    (txpnt_wb[31:0], len[15:0], negated_crc);
 
  check_tx_crc
 
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
 
 
 
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
 
  --------------------------------------------------------------------------------
 
  append_rx_crc
 
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
 
  */
 
 
 
//////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test receive packet synchronization with receive          ////
////  test_mac_full_duplex_receive:                               ////
 
////                                                              ////
 
////  0: Test no receive when all buffers are TX ( 10Mbps ).      ////
 
////  1: Test no receive when all buffers are TX ( 100Mbps ).     ////
 
////  2: Test receive packet synchronization with receive         ////
 
////     disable/enable ( 10Mbps ).                               ////
 
////  3: Test receive packet synchronization with receive         ////
  ////  disable/enable ( 100Mbps ).                               ////
  ////  disable/enable ( 100Mbps ).                               ////
 
////  4: Test receive packets from MINFL to MAXFL sizes at        ////
 
////     one RX buffer decriptor ( 10Mbps ).                      ////
 
////  5: Test receive packets from MINFL to MAXFL sizes at        ////
 
////     one RX buffer decriptor ( 100Mbps ).                     ////
  ////                                                            ////
  ////                                                            ////
 
//////////////////////////////////////////////////////////////////////
 
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
 
begin
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 3) //
  ////                                                            ////
 
  ////  Test no receive when all buffers are TX ( 10Mbps ).       ////
 
  ////                                                            ////
 
  ////////////////////////////////////////////////////////////////////
 
  if (test_num == 0) //
  begin
  begin
    // TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
    // TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
    test_name   = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
    test_name   = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
    `TIME; $display("  TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
    `TIME; $display("  TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
 
 
    // unmask interrupts
    // unmask interrupts
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
    // set all buffer descriptors to TX - must be set before RX enable
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
    // enable RX, set full-duplex mode, receive small, NO correct IFG
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
              `ETH_MODER_PRO | `ETH_MODER_BRO,
              `ETH_MODER_PRO | `ETH_MODER_BRO,
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // prepare two packets of MAXFL length
 
    wait (wbm_working == 0);
    // write to phy's control register for 10Mbps
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    min_tmp = tmp[31:16];
    speed = 10;
    st_data = 8'h0F;
 
 
    i = 0;
 
    while (i < 128)
 
    begin
 
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
 
      begin
 
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
 
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
 
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
 
      end
 
      set_rx_bd_wrap(i);
 
      set_rx_bd_empty(0, i);
 
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
 
      begin
 
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
 
        repeat(10) @(posedge mrx_clk);
 
      end
 
      @(posedge mrx_clk);
 
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
 
      begin
 
        check_rx_bd(0, tmp);
 
        #1;
 
        if (tmp[15] === 1'b0)
 
        begin
 
          test_fail("Receive should not start at all");
 
          fail = fail + 1;
 
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
 
        end
 
        if (tmp[7:0] !== 0)
 
        begin
 
          test_fail("Receive should not be finished since it should not start at all");
 
          fail = fail + 1;
 
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
 
        end
 
        @(posedge wb_clk);
 
      end
 
      wait (wbm_working == 0);
 
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
      if (tmp[6:0] !== 0)
 
      begin
 
        test_fail("Receive should not get INT since it should not start at all");
 
        fail = fail + 1;
 
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
 
      end
 
      clear_rx_bd(0, i);
 
      if ((i < 5) || (i > 124))
 
        i = i + 1;
 
      else
 
        i = i + 120;
 
    end
 
    // disable RX
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
 
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    if(fail == 0)
 
      test_ok;
 
    else
 
      fail = 0;
 
  end
 
 
 
 
 
  ////////////////////////////////////////////////////////////////////
 
  ////                                                            ////
 
  ////  Test no receive when all buffers are TX ( 100Mbps ).      ////
 
  ////                                                            ////
 
  ////////////////////////////////////////////////////////////////////
 
  if (test_num == 1) //
 
  begin
 
    // TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
 
    test_name   = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
 
    `TIME; $display("  TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
 
 
 
    // unmask interrupts
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // set all buffer descriptors to TX - must be set before RX enable
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // enable RX, set full-duplex mode, receive small, NO correct IFG
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
 
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
 
 
    // write to phy's control register for 100Mbps
 
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
 
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
 
    speed = 100;
 
 
 
    i = 0;
 
    while (i < 128)
 
    begin
 
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
 
      begin
 
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
 
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
 
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
 
      end
 
      set_rx_bd_wrap(i);
 
      set_rx_bd_empty(0, i);
 
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
 
      begin
 
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
 
        repeat(10) @(posedge mrx_clk);
 
      end
 
      @(posedge mrx_clk);
 
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
 
      begin
 
        check_rx_bd(0, tmp);
 
        #1;
 
        if (tmp[15] === 1'b0)
 
        begin
 
          test_fail("Receive should not start at all");
 
          fail = fail + 1;
 
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
 
        end
 
        if (tmp[7:0] !== 0)
 
        begin
 
          test_fail("Receive should not be finished since it should not start at all");
 
          fail = fail + 1;
 
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
 
        end
 
        @(posedge wb_clk);
 
      end
 
      wait (wbm_working == 0);
 
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
      if (tmp[6:0] !== 0)
 
      begin
 
        test_fail("Receive should not get INT since it should not start at all");
 
        fail = fail + 1;
 
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
 
      end
 
      clear_rx_bd(0, i);
 
      if ((i < 5) || (i > 124))
 
        i = i + 1;
 
      else
 
        i = i + 120;
 
    end
 
    // disable RX
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
 
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    if(fail == 0)
 
      test_ok;
 
    else
 
      fail = 0;
 
  end
 
 
 
 
 
  ////////////////////////////////////////////////////////////////////
 
  ////                                                            ////
 
  ////  Test receive packet synchronization with receive          ////
 
  ////  disable/enable ( 10Mbps ).                                ////
 
  ////                                                            ////
 
  ////////////////////////////////////////////////////////////////////
 
  if (test_num == 2) //
 
  begin
 
    // TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
 
    test_name   = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
 
    `TIME; $display("  TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
 
 
 
    // unmask interrupts
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
 
              `ETH_MODER_PRO | `ETH_MODER_BRO,
 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // prepare two packets of MAXFL length
 
    wait (wbm_working == 0);
 
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
 
    min_tmp = tmp[31:16];
 
    st_data = 8'h0F;
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
    st_data = 8'h1A;
    st_data = 8'h1A;
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
Line 11930... Line 12186...
    begin
    begin
      test_fail("WB INT signal should not be set");
      test_fail("WB INT signal should not be set");
      fail = fail + 1;
      fail = fail + 1;
    end
    end
 
 
    // write to phy's control register for 100Mbps
    // write to phy's control register for 10Mbps
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
    speed = 100;
    speed = 10;
 
 
    frame_started = 0;
    frame_started = 0;
    frame_ended = 0;
    frame_ended = 0;
    wait_for_frame = 0;
    wait_for_frame = 0;
    check_frame = 0;
    check_frame = 0;
Line 12024... Line 12280...
          begin
          begin
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
          end
          end
        end
        end
        begin: send_packet1
        begin: send_packet0
          wait (MRxDV === 1'b1); // start transmit
          wait (MRxDV === 1'b1); // start transmit
          wait (MRxDV === 1'b0); // end transmit
          wait (MRxDV === 1'b0); // end transmit
          check_frame = 1;
          check_frame = 1;
          repeat(10) @(posedge mrx_clk);
          repeat(10) @(posedge mrx_clk);
          repeat(15) @(posedge wb_clk);
          repeat(15) @(posedge wb_clk);
Line 12258... Line 12514...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
  ////  Test receive packet synchronization with receive          ////
  ////  one RX buffer decriptor ( 10Mbps ).                       ////
  ////  disable/enable ( 100Mbps ).                               ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 4) // 
  if (test_num == 3) //
  begin
  begin
    // TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
    // TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
    test_name   = "TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )";
    test_name   = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
    `TIME; $display("  TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )");
    `TIME; $display("  TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
 
 
    // unmask interrupts
    // unmask interrupts
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
              `ETH_MODER_PRO,// | `ETH_MODER_BRO, 
              `ETH_MODER_PRO | `ETH_MODER_BRO,
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // prepare two packets of MAXFL length
    // prepare two packets of MAXFL length
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    min_tmp = tmp[31:16];
    min_tmp = tmp[31:16];
    st_data = 8'h0F;
    st_data = 8'h0F;
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
 
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
    st_data = 8'h1A;
    st_data = 8'h1A;
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
 
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
    // check WB INT signal
    // check WB INT signal
    if (wb_int !== 1'b0)
    if (wb_int !== 1'b0)
    begin
    begin
      test_fail("WB INT signal should not be set");
      test_fail("WB INT signal should not be set");
      fail = fail + 1;
      fail = fail + 1;
    end
    end
 
 
    // write to phy's control register for 10Mbps
    // write to phy's control register for 100Mbps
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    speed = 10;
    speed = 100;
 
 
    i_length = (min_tmp - 4);
    frame_started = 0;
    while (i_length <= (max_tmp - 4))
    frame_ended = 0;
 
    wait_for_frame = 0;
 
    check_frame = 0;
 
    stop_checking_frame = 0;
 
    first_fr_received = 1; // at the beginning the first frame of each two will be received!
 
 
 
    num_of_frames = 0; // 
 
    num_of_bd = 0;
 
    i_length = (min_tmp + 1); // 5 bytes longer than MINFL
 
    while (i_length < (max_tmp - 4))
    begin
    begin
      // choose generating carrier sense and collision for first and last 64 lengths of frames
      // choose generating carrier sense and collision 
      case (i_length[1:0])
      case (num_of_frames[1:0])
      2'h0: // Interrupt is generated
      2'h0: // Interrupt is generated
      begin
      begin
        // enable interrupt generation
        // enable interrupt generation
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
        // unmask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
        // not detect carrier sense in FD and no collision
        // not detect carrier sense in FD and no collision
        eth_phy.no_carrier_sense_rx_fd_detect(0);
        eth_phy.no_carrier_sense_rx_fd_detect(0);
        eth_phy.collision(0);
        eth_phy.collision(0);
      end
      end
      2'h1: // Interrupt is not generated
      2'h1: // Interrupt is generated
      begin
      begin
        // enable interrupt generation
        // enable interrupt generation
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
        // mask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
        // detect carrier sense in FD and no collision
        // detect carrier sense in FD and no collision
        eth_phy.no_carrier_sense_rx_fd_detect(1);
        eth_phy.no_carrier_sense_rx_fd_detect(1);
        eth_phy.collision(0);
        eth_phy.collision(0);
      end
      end
      2'h2: // Interrupt is not generated
      2'h2: // Interrupt is generated
      begin
      begin
        // disable interrupt generation
        // disable interrupt generation
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
        // unmask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
        // not detect carrier sense in FD and set collision
        // not detect carrier sense in FD and set collision
        eth_phy.no_carrier_sense_rx_fd_detect(0);
        eth_phy.no_carrier_sense_rx_fd_detect(0);
        eth_phy.collision(1);
        eth_phy.collision(1);
      end
      end
      default: // 2'h3: // Interrupt is not generated
      default: // 2'h3: // Interrupt is generated
      begin
      begin
        // disable interrupt generation
        // disable interrupt generation
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
        // mask interrupts
 
        wait (wbm_working == 0);
 
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
        // detect carrier sense in FD and set collision
        // detect carrier sense in FD and set collision
        eth_phy.no_carrier_sense_rx_fd_detect(1);
        eth_phy.no_carrier_sense_rx_fd_detect(1);
        eth_phy.collision(1);
        eth_phy.collision(1);
      end
      end
      endcase
      endcase
      if (i_length[0] == 1'b0)
 
        append_rx_crc (0, i_length, 1'b0, 1'b0);
 
      else
 
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
 
      // set wrap bit
      // set wrap bit
      set_rx_bd_wrap(127);
      set_rx_bd_wrap(118);
      set_rx_bd_empty(127, 127);
      set_rx_bd_empty(118, 118);
 
      check_frame = 0;
 
      stop_checking_frame = 0;
 
      tmp_data = 0;
      fork
      fork
 
        begin // enable RX MAC on first of each two packets - every second should be recived normaly
 
          if (num_of_frames[0] == 1'b0)
        begin
        begin
          if (i_length[0] == 1'b0)
            repeat(1) @(posedge wb_clk);
 
            if (num_of_frames[1] == 1'b0)
 
            begin
 
              repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
 
            end
 
            else
 
            begin
 
              @(posedge mrx_clk);
 
              repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
 
            end
 
            // enable RX, set full-duplex mode, NO receive small, NO correct IFG
 
            wbm_init_waits = 4'h0;
 
            wbm_subseq_waits = 4'h0;
 
            #1 wait (wbm_working == 0);
 
            wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
 
                      `ETH_MODER_PRO | `ETH_MODER_BRO,
 
                      4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
 
          end
 
        end
 
        begin // send a packet from PHY RX
 
          repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
 
          if (num_of_frames[1] == 1'b0)
 
          begin
 
            set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
 
          end
          else
          else
 
          begin
 
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
 
          end
 
        end
 
        begin: send_packet1
 
          wait (MRxDV === 1'b1); // start transmit
 
          wait (MRxDV === 1'b0); // end transmit
 
          check_frame = 1;
          repeat(10) @(posedge mrx_clk);
          repeat(10) @(posedge mrx_clk);
 
          repeat(15) @(posedge wb_clk);
 
          stop_checking_frame = 1;
        end
        end
 
        begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
 
          @(posedge eth_sl_wb_ack_o or posedge MRxDV);
 
          if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
        begin
        begin
          #1 check_rx_bd(127, data);
            tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
          if (i_length < min_tmp) // just first four
          end
 
          else if (MRxDV === 1'b1)
          begin
          begin
            while (data[15] === 1)
            while (eth_sl_wb_ack_o === 1'b0)
            begin
            begin
              #1 check_rx_bd(127, data);
 
              @(posedge wb_clk);
              @(posedge wb_clk);
 
              tmp_data = tmp_data + 1;
            end
            end
            repeat (1) @(posedge wb_clk);
            tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
          end
          end
          else
          else if (eth_sl_wb_ack_o === 1'b1)
          begin
          begin
            wait (MRxDV === 1'b1); // start transmit
            @(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
            #1 check_rx_bd(127, data);
            while (MRxDV === 1'b0)
            if (data[15] !== 1)
 
            begin
            begin
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
              @(posedge wb_clk);
              fail = fail + 1;
              tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
            end
            end
            wait (MRxDV === 1'b0); // end transmit
          end
            while (data[15] === 1)
        end
 
        begin // check packet
 
          wait (check_frame == 1);
 
          check_rx_bd(118, tmp_bd);
 
          while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
            begin
            begin
              #1 check_rx_bd(127, data);
            #1 check_rx_bd(118, tmp_bd);
              @(posedge wb_clk);
              @(posedge wb_clk);
            end
            end
            repeat (1) @(posedge wb_clk);
          if (num_of_frames[0] == 1'b0)
 
          begin
 
            if (tmp_bd[15] === 1)
 
            begin
 
              if (first_fr_received == 1)
 
              begin
 
                first_fr_received = 0;
 
                $display("    %0d packets (without this one) are checked - packets are received by two in a set",
 
                         num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
 
                $display("    From this moment:");
 
                $display("    first one of two packets (including this one) is not accepted due to late RX enable");
 
                if (tmp_data[31])
 
                  $display("    ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
 
                else
 
                  $display("    ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
 
              end
 
              // check FB, etc.
 
              if (tmp_bd[31:0] !== 32'h0000_E000)
 
              begin
 
                `TIME; $display("*E RX buffer descriptor status of NOT received packet is not correct: %0h", tmp_bd[31:0]);
 
                test_fail("RX buffer descriptor status of NOT received packet is not correct");
 
                fail = fail + 1;
 
              end
 
            end
 
            // else // (tmp_bd[15] === 0) - check FB, packet, etc.
 
          end
 
          else // (num_of_frames[0] == 1'b1)
 
          begin
 
            if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
 
            begin // check NOTHING
 
                `TIME; $display("*E RX packet should be accepted, buffer descriptor is not correct: %0h", tmp_bd[31:0]);
 
                test_fail("RX packet should be accepted, buffer descriptor is not correct");
 
                fail = fail + 1;
 
            end
 
            // else // (tmp_bd[15] === 0) - check FB, packet, etc.
          end
          end
 
          if (stop_checking_frame == 0)
 
            disable send_packet1;
        end
        end
      join
      join
 
      // ONLY IF packet was received!
 
      if (tmp_bd[15] === 0)
 
      begin
      // check length of a PACKET
      // check length of a PACKET
      if (data[31:16] != (i_length + 4))
        if (tmp_bd[31:16] != (i_length + 4))
      begin
      begin
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
                        data[31:16], (i_length + 4));
                          tmp_bd[31:16], (i_length + 4));
        test_fail("Wrong length of the packet out from PHY");
        test_fail("Wrong length of the packet out from PHY");
        fail = fail + 1;
        fail = fail + 1;
      end
      end
      // checking in the following if statement is performed only for first and last 64 lengths
 
      // check received RX packet data and CRC
      // check received RX packet data and CRC
      if (i_length[0] == 1'b0)
        if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
      begin
      begin
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
          if (num_of_frames[1] == 1'b0)
 
          begin
 
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
      end
      end
      else
      else
      begin
      begin
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
      end
      end
      if (tmp > 0)
      if (tmp > 0)
      begin
      begin
        `TIME; $display("*E Wrong data of the received packet");
        `TIME; $display("*E Wrong data of the received packet");
        test_fail("Wrong data of the received packet");
        test_fail("Wrong data of the received packet");
        fail = fail + 1;
        fail = fail + 1;
      end
      end
      // check WB INT signal
        end
      if (i_length[1:0] == 2'h0)
        else // if PREVIOUS RX buffer descriptor was ready
      begin
      begin
        if (wb_int !== 1'b1)
          if (num_of_frames[1] == 1'b0)
        begin
        begin
          `TIME; $display("*E WB INT signal should be set");
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
          test_fail("WB INT signal should be set");
          end
 
          else
 
          begin
 
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
 
          end
 
          if (tmp > 0)
 
          begin
 
            `TIME; $display("*E Wrong data of the received packet");
 
            test_fail("Wrong data of the received packet");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      else
      end
 
      // check WB INT signal
 
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
      begin
      begin
        if (wb_int !== 1'b0)
        if (wb_int !== 1'b0)
        begin
        begin
          `TIME; $display("*E WB INT signal should not be set");
          `TIME; $display("*E WB INT signal should not be set");
          test_fail("WB INT signal should not be set");
          test_fail("WB INT signal should not be set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      // check RX buffer descriptor of a packet
      else
      check_rx_bd(127, data);
 
      if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
 
      begin
      begin
        if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
        if (wb_int !== 1'b1)
             ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
        begin
 
          `TIME; $display("*E WB INT signal should be set");
 
          test_fail("WB INT signal should be set");
 
          fail = fail + 1;
 
        end
 
      end
 
      // check RX buffer descriptor of a packet - only 15 LSBits
 
      check_rx_bd(118, data);
 
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
 
      begin
 
        if (data[15:0] !== 16'hE000)
        begin
        begin
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
          test_fail("RX buffer descriptor status is not correct");
          test_fail("RX buffer descriptor status is not correct");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      else // interrupt not enabled
      else // interrupt enabled
      begin
      begin
        if ( ((data[15:0] !== 16'h2080) && (i_length[0] == 1'b0)) ||
        if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
             ((data[15:0] !== 16'h2080) && (i_length[0] == 1'b1)) )
 
        begin
        begin
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
          test_fail("RX buffer descriptor status is not correct");
          test_fail("RX buffer descriptor status is not correct");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      // clear RX buffer descriptor for first 4 frames
 
      if (i_length < min_tmp)
 
        clear_rx_bd(127, 127);
 
      // check interrupts
      // check interrupts
      wait (wbm_working == 0);
      wait (wbm_working == 0);
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
 
      begin
 
        if (data !== 0)
 
        begin
 
          `TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
 
          test_fail("Any of interrupts was set");
 
          fail = fail + 1;
 
        end
 
      end
 
      else
      begin
      begin
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
        begin
        begin
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
          test_fail("Interrupt Receive Buffer was not set");
          test_fail("Interrupt Receive Buffer was not set");
Line 12484... Line 12842...
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
          test_fail("Other interrupts (except Receive Buffer) were set");
          test_fail("Other interrupts (except Receive Buffer) were set");
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      else
 
      begin
 
        if (data !== 0)
 
        begin
 
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
 
          test_fail("Any of interrupts (except Receive Buffer) was set");
 
          fail = fail + 1;
 
        end
 
      end
 
      // clear interrupts
      // clear interrupts
      wait (wbm_working == 0);
      wait (wbm_working == 0);
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
      // check WB INT signal
      // check WB INT signal
      if (wb_int !== 1'b0)
      if (wb_int !== 1'b0)
      begin
      begin
        test_fail("WB INT signal should not be set");
        test_fail("WB INT signal should not be set");
        fail = fail + 1;
        fail = fail + 1;
      end
      end
      // INTERMEDIATE DISPLAYS
      // disable RX after two packets
      if ((i_length + 4) == (min_tmp + 64))
      if (num_of_frames[0] == 1'b1)
      begin
      begin
        // starting length is min_tmp, ending length is (min_tmp + 64)
        // disable RX, set full-duplex mode, NO receive small, NO correct IFG
        $display("    receive small packets is NOT selected");
 
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
 
                 min_tmp, (min_tmp + 64));
 
        // set receive small, remain the rest
 
        wait (wbm_working == 0);
        wait (wbm_working == 0);
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
        wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
                  4'hF, 1, 4'h0, 4'h0); // write ASAP
      end
      end
      else if ((i_length + 4) == (max_tmp - 16))
      // the number of frame transmitted
      begin
      num_of_frames = num_of_frames + 1;
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
      num_of_bd = 0;
        $display("    receive small packets is selected");
      // set length (LOOP variable)
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
      if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
                 (min_tmp + 64 + 128), tmp_data);
        i_length = (max_tmp - 4);
        // reset receive small, remain the rest
      @(posedge wb_clk);
 
    end
 
    // disable RX
        wait (wbm_working == 0);
        wait (wbm_working == 0);
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
 
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
      end
 
      else if ((i_length + 4) == max_tmp)
 
      begin
 
        $display("    receive small packets is NOT selected");
 
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
 
                 (max_tmp - (4 + 16)), max_tmp);
 
      end
 
      // set length (loop variable)
 
      if ((i_length + 4) < (min_tmp + 64))
 
        i_length = i_length + 1;
 
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
 
      begin
 
        i_length = i_length + 128;
 
        tmp_data = i_length + 4; // last tmp_data is ending length
 
      end
 
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
 
        i_length = max_tmp - (4 + 16);
 
      else if ((i_length + 4) >= (max_tmp - 16))
 
        i_length = i_length + 1;
 
      else
 
      begin
 
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
 
        #10 $stop;
 
      end
 
    end
 
    // disable RX
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
 
              `ETH_MODER_PRO | `ETH_MODER_BRO,
              `ETH_MODER_PRO | `ETH_MODER_BRO,
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    if(fail == 0)
    if(fail == 0)
      test_ok;
      test_ok;
    else
    else
Line 12565... Line 12882...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
  ////  Test receive packets from MINFL to MAXFL sizes at         ////
  ////  one RX buffer decriptor ( 100Mbps ).                      ////
  ////  one RX buffer decriptor ( 10Mbps ).                       ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 5) //
  if (test_num == 4) // 
  begin
  begin
    // TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
    // TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
    test_name   = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
    test_name   = "TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )";
    `TIME; $display("  TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
    `TIME; $display("  TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )");
 
 
    // unmask interrupts
    // unmask interrupts
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
Line 12585... Line 12902...
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
              `ETH_MODER_PRO | `ETH_MODER_BRO,
              `ETH_MODER_PRO,// | `ETH_MODER_BRO, 
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // prepare two packets of MAXFL length
    // prepare two packets of MAXFL length
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    min_tmp = tmp[31:16];
    min_tmp = tmp[31:16];
    st_data = 8'h0F;
    st_data = 8'h0F;
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'hAA02_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
    st_data = 8'h1A;
    st_data = 8'h1A;
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
    // check WB INT signal
    // check WB INT signal
    if (wb_int !== 1'b0)
    if (wb_int !== 1'b0)
    begin
    begin
      test_fail("WB INT signal should not be set");
      test_fail("WB INT signal should not be set");
      fail = fail + 1;
      fail = fail + 1;
    end
    end
 
 
    // write to phy's control register for 100Mbps
    // write to phy's control register for 10Mbps
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
    speed = 100;
    speed = 10;
 
 
    i_length = (min_tmp - 4);
    i_length = (min_tmp - 4);
    while (i_length <= (max_tmp - 4))
    while (i_length <= (max_tmp - 4))
    begin
    begin
      // choose generating carrier sense and collision for first and last 64 lengths of frames
      // choose generating carrier sense and collision for first and last 64 lengths of frames
Line 12750... Line 13067...
          fail = fail + 1;
          fail = fail + 1;
        end
        end
      end
      end
      // check RX buffer descriptor of a packet
      // check RX buffer descriptor of a packet
      check_rx_bd(127, data);
      check_rx_bd(127, data);
      if (i_length[1] == 1'b0) // interrupt enabled 
      if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
      begin
      begin
        if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
        if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
             ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
             ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
        begin
        begin
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
Line 12872... Line 13189...
  end
  end
 
 
 
 
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////                                                            ////
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
  ////  Test receive packets from MINFL to MAXFL sizes at         ////
  ////  maximum RX buffer decriptors ( 10Mbps ).                  ////
  ////  one RX buffer decriptor ( 100Mbps ).                      ////
  ////                                                            ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 6) // 
  if (test_num == 5) //
  begin
  begin
    // TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
    // TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
    test_name = "TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )";
    test_name   = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
    `TIME; $display("  TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )");
    `TIME; $display("  TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
    // set maximum RX buffer descriptors (128) - must be set before RX enable
 
 
    // unmask interrupts
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
 
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
 
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
 
    wait (wbm_working == 0);
 
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
              `ETH_MODER_PRO | `ETH_MODER_BRO,
              `ETH_MODER_PRO | `ETH_MODER_BRO,
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    // prepare two packets of MAXFL length
    // prepare two packets of MAXFL length
    wait (wbm_working == 0);
    wait (wbm_working == 0);
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
    min_tmp = tmp[31:16];
    min_tmp = tmp[31:16];
    st_data = 8'hAC;
    st_data = 8'h0F;
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
    st_data = 8'h35;
    st_data = 8'h1A;
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
    num_of_frames = 0;
 
    num_of_bd = 0;
 
    // check WB INT signal
    // check WB INT signal
    if (wb_int !== 1'b0)
    if (wb_int !== 1'b0)
    begin
    begin
      test_fail("WB INT signal should not be set");
      test_fail("WB INT signal should not be set");
      fail = fail + 1;
      fail = fail + 1;
    end
    end
 
 
    // write to phy's control register for 10Mbps
    // write to phy's control register for 100Mbps
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
    speed = 10;
    speed = 100;
 
 
    i_length = (min_tmp - 4);
    i_length = (min_tmp - 4);
    while (i_length <= (max_tmp - 4))
    while (i_length <= (max_tmp - 4))
    begin
    begin
      // append CRC to packet
      // choose generating carrier sense and collision for first and last 64 lengths of frames
      if (i_length[0] == 1'b0)
 
        append_rx_crc (0, i_length, 1'b0, 1'b0);
 
      else
 
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
 
      // choose generating carrier sense and collision
 
      case (i_length[1:0])
      case (i_length[1:0])
      2'h0: // Interrupt is generated
      2'h0: // Interrupt is generated
      begin
      begin
        // Reset_tx_bd nable interrupt generation
        // enable interrupt generation
 
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
        // unmask interrupts
        // unmask interrupts
        wait (wbm_working == 0);
        wait (wbm_working == 0);
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
        // not detect carrier sense in FD and no collision
        // not detect carrier sense in FD and no collision
        eth_phy.no_carrier_sense_rx_fd_detect(0);
        eth_phy.no_carrier_sense_rx_fd_detect(0);
        eth_phy.collision(0);
        eth_phy.collision(0);
      end
      end
      2'h1: // Interrupt is not generated
      2'h1: // Interrupt is not generated
      begin
      begin
        // set_tx_bd enable interrupt generation
        // enable interrupt generation
 
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
        // mask interrupts
        // mask interrupts
        wait (wbm_working == 0);
        wait (wbm_working == 0);
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);