| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.33 2005/02/21 13:02:13 igorm
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// Tests for delayed CRC and defer indication added.
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//
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// Revision 1.32 2004/03/26 15:59:21 tadejm
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// Revision 1.32 2004/03/26 15:59:21 tadejm
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// Latest Ethernet IP core testbench.
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// Latest Ethernet IP core testbench.
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//
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//
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// Revision 1.31 2003/12/05 12:46:26 tadejm
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// Revision 1.31 2003/12/05 12:46:26 tadejm
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// Updated testbench. Some more testcases, some repaired.
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// Updated testbench. Some more testcases, some repaired.
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| Line 510... |
Line 513... |
test_mac_full_duplex_transmit(0, 23); // 0 - 23
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test_mac_full_duplex_transmit(0, 23); // 0 - 23
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test_mac_full_duplex_receive(0, 15); // 0 - 15
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test_mac_full_duplex_receive(0, 15); // 0 - 15
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test_mac_full_duplex_flow_control(0, 5); // 0 - 5
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test_mac_full_duplex_flow_control(0, 5); // 0 - 5
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test_mac_half_duplex_flow(0, 1);
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test_mac_half_duplex_flow(0, 1);
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// Tests not working, yet.
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// test_mac_half_duplex_flow(0, 0); // 2, 3, 4, 5 These tests need to be fixed !!!
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$display("");
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$display("");
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$display("===========================================================================");
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$display("===========================================================================");
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$display("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
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$display("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
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$display("===========================================================================");
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$display("===========================================================================");
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test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
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test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
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eth_phy.carrier_sense_real_delay(1);
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eth_phy.carrier_sense_real_delay(1);
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test_mac_full_duplex_transmit(0, 21); // 0 - 21
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test_mac_full_duplex_transmit(0, 23); // 0 - 23
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test_mac_full_duplex_receive(0, 13); // 0 - 13
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test_mac_full_duplex_receive(0, 15); // 0 - 15
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test_mac_full_duplex_flow_control(0, 5); // 0 - 5
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test_mac_full_duplex_flow_control(0, 5); // 0 - 5
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test_mac_half_duplex_flow(0, 1);
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test_mac_half_duplex_flow(0, 1);
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// Finish test's logs
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// Finish test's logs
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| Line 2208... |
Line 2215... |
// check the BUSY signal to see if the bus is still IDLE
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// check the BUSY signal to see if the bus is still IDLE
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for (i1 = 0; i1 < 8; i1 = i1 + 1)
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for (i1 = 0; i1 < 8; i1 = i1 + 1)
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check_mii_busy; // wait for bus to become idle
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check_mii_busy; // wait for bus to become idle
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// try normal write or read after read was finished
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// try normal write or read after read was finished
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#Tp phy_data = {8'h7D, (i[7:0] + 1)};
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#Tp phy_data = {8'h7D, (i[7:0] + 1'b1)};
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#Tp cnt = 0;
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#Tp cnt = 0;
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if (i3 == 0) // write after read
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if (i3 == 0) // write after read
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begin
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begin
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// write request
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// write request
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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| Line 2344... |
Line 2351... |
// set address
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// set address
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reg_addr = 5'h0; // control register
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reg_addr = 5'h0; // control register
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phy_addr = 5'h1; // correct PHY address
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phy_addr = 5'h1; // correct PHY address
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cnt = 0;
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cnt = 0;
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// write request
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// write request
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phy_data = {8'h75, (i[7:0] + 1)};
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phy_data = {8'h75, (i[7:0] + 1'b1)};
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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fork
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fork
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begin
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begin
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repeat(i) @(posedge Mdc_O);
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repeat(i) @(posedge Mdc_O);
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// write command 0x0 into MII command register
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// write command 0x0 into MII command register
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| Line 2391... |
Line 2398... |
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// try normal write or read after write was finished
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// try normal write or read after write was finished
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#Tp cnt = 0;
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#Tp cnt = 0;
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if (i3 == 0) // write after write
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if (i3 == 0) // write after write
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begin
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begin
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phy_data = {8'h7A, (i[7:0] + 1)};
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phy_data = {8'h7A, (i[7:0] + 1'b1)};
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// write request
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// write request
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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// wait for serial bus to become active
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// wait for serial bus to become active
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wait(Mdio_IO !== 1'bz);
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wait(Mdio_IO !== 1'bz);
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// count transfer length
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// count transfer length
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| Line 3856... |
Line 3863... |
// check the BUSY signal to see if the bus is still IDLE
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// check the BUSY signal to see if the bus is still IDLE
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for (i1 = 0; i1 < 8; i1 = i1 + 1)
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for (i1 = 0; i1 < 8; i1 = i1 + 1)
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check_mii_busy; // wait for bus to become idle
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check_mii_busy; // wait for bus to become idle
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// try normal write or read after scan was finished
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// try normal write or read after scan was finished
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phy_data = {8'h7D, (i[7:0] + 1)};
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phy_data = {8'h7D, (i[7:0] + 1'b1)};
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cnt = 0;
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cnt = 0;
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if (i3 == 0) // write after scan
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if (i3 == 0) // write after scan
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begin
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begin
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// write request
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// write request
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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| Line 4121... |
Line 4128... |
// check the BUSY signal to see if the bus is still IDLE
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// check the BUSY signal to see if the bus is still IDLE
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for (i1 = 0; i1 < 8; i1 = i1 + 1)
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for (i1 = 0; i1 < 8; i1 = i1 + 1)
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check_mii_busy; // wait for bus to become idle
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check_mii_busy; // wait for bus to become idle
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// try normal write or read after scan was finished
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// try normal write or read after scan was finished
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phy_data = {8'h7D, (i[7:0] + 1)};
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phy_data = {8'h7D, (i[7:0] + 1'b1)};
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cnt = 0;
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cnt = 0;
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if (i3 == 0) // write after scan
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if (i3 == 0) // write after scan
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begin
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begin
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// write request
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// write request
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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| Line 19591... |
Line 19598... |
end
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end
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end
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end
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end
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end
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else
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else
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begin
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begin
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#200;
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if(!MTxEn) // Pause frame was not received because RxFlow is turned off.
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if(!MTxEn) // Pause frame was not received because RxFlow is turned off.
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begin
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begin
|
`TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
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`TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
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test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
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test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
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fail = fail + 1;
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fail = fail + 1;
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