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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Diff between revs 343 and 344
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| Rev 343 |
Rev 344 |
| Line 2398... |
Line 2398... |
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// try normal write or read after write was finished
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// try normal write or read after write was finished
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#Tp cnt = 0;
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#Tp cnt = 0;
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if (i3 == 0) // write after write
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if (i3 == 0) // write after write
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begin
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begin
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phy_data = {8'h7A, (i[7:0] + 1'b1)};
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phy_data = {8'h78, (i[7:0] + 1'b1)};
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// write request
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// write request, bit 9 in phy_data is self-clearing
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#Tp mii_write_req(phy_addr, reg_addr, phy_data);
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#Tp mii_write_req(phy_addr, reg_addr, (phy_data|16'h0200));
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// wait for serial bus to become active
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// wait for serial bus to become active
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wait(Mdio_IO !== 1'bz);
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wait(Mdio_IO !== 1'bz);
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// count transfer length
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// count transfer length
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while(Mdio_IO !== 1'bz)
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while(Mdio_IO !== 1'bz)
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begin
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begin
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