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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Diff between revs 343 and 344

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Rev 343 Rev 344
Line 2398... Line 2398...
 
 
          // try normal write or read after write was finished
          // try normal write or read after write was finished
          #Tp cnt = 0;
          #Tp cnt = 0;
          if (i3 == 0) // write after write
          if (i3 == 0) // write after write
          begin
          begin
            phy_data = {8'h7A, (i[7:0] + 1'b1)};
            phy_data = {8'h78, (i[7:0] + 1'b1)};
            // write request
            // write request, bit 9 in phy_data is self-clearing
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
            #Tp mii_write_req(phy_addr, reg_addr, (phy_data|16'h0200));
            // wait for serial bus to become active
            // wait for serial bus to become active
            wait(Mdio_IO !== 1'bz);
            wait(Mdio_IO !== 1'bz);
            // count transfer length
            // count transfer length
            while(Mdio_IO !== 1'bz)
            while(Mdio_IO !== 1'bz)
            begin
            begin

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