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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Diff between revs 346 and 348

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Rev 346 Rev 348
Line 436... Line 436...
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
  $fdisplay(wb_m_mon_log_file_desc, " ");
  $fdisplay(wb_m_mon_log_file_desc, " ");
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
  $fdisplay(wb_m_mon_log_file_desc, " ");
  $fdisplay(wb_m_mon_log_file_desc, " ");
 
 
 
`ifdef VCD
 
   $dumpfile("../build/sim/ethmac.vcd");
 
   $dumpvars(0);
 
`endif
  // Reset pulse
  // Reset pulse
  wb_rst =  1'b1;
  wb_rst =  1'b1;
  #423 wb_rst =  1'b0;
  #423 wb_rst =  1'b0;
 
 
  // Clear memories
  // Clear memories

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