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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_clockgen.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 68... Line 68...
 
 
`include "timescale.v"
`include "timescale.v"
 
 
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
 
 
parameter Tp=1;
 
 
 
input       Clk;              // Input clock (Host clock)
input       Clk;              // Input clock (Host clock)
input       Reset;            // Reset signal
input       Reset;            // Reset signal
input [7:0] Divider;          // Divider (input clock will be divided by the Divider[7:0])
input [7:0] Divider;          // Divider (input clock will be divided by the Divider[7:0])
 
 
output      Mdc;              // Output clock
output      Mdc;              // Output clock
Line 94... Line 92...
 
 
// Counter counts half period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    Counter[7:0] <= #Tp 8'h1;
    Counter[7:0] <=  8'h1;
  else
  else
    begin
    begin
      if(CountEq0)
      if(CountEq0)
        begin
        begin
          Counter[7:0] <= #Tp CounterPreset[7:0];
          Counter[7:0] <=  CounterPreset[7:0];
        end
        end
      else
      else
        Counter[7:0] <= #Tp Counter - 8'h1;
        Counter[7:0] <=  Counter - 8'h1;
    end
    end
end
end
 
 
 
 
// Mdc is asserted every other half period
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    Mdc <= #Tp 1'b0;
    Mdc <=  1'b0;
  else
  else
    begin
    begin
      if(CountEq0)
      if(CountEq0)
        Mdc <= #Tp ~Mdc;
        Mdc <=  ~Mdc;
    end
    end
end
end
 
 
 
 
assign CountEq0 = Counter == 8'h0;
assign CountEq0 = Counter == 8'h0;

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