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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Diff between revs 129 and 160

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Rev 129 Rev 160
Line 39... Line 39...
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//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2002/08/14 17:16:07  mohor
 
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
 
// interfaces:
 
// - Host connects to the master interface
 
// - Ethernet master (DMA) connects to the second master interface
 
// - Memory interface connects to the slave interface
 
// - Ethernet slave interface (access to registers and BDs) connects to second
 
//   slave interface
 
//
//
//
//
//
//
//
//
//
 
 
Line 334... Line 343...
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
    end
    end
    else if(s1_wb_cyc_o) begin
    else if(s2_wb_cyc_o) begin
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
    end
    end
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    $stop;
    $stop;
  end
  end
end
end
 
 
 
 
 
always @ (posedge wb_clk_i)
 
begin
 
  if(s1_wb_err_i & s1_wb_cyc_o) begin
 
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
 
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
 
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
 
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
 
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
 
    $stop;
 
  end
 
  if(s2_wb_err_i & s2_wb_cyc_o) begin
 
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
 
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
 
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
 
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
 
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
 
    $stop;
 
  end
 
end
 
 
 
 
 
 
endmodule
endmodule
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