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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Diff between revs 350 and 351

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Rev 350 Rev 351
Line 59... Line 59...
//
//
//
//
//
//
//
//
 
 
`include "eth_defines.v"
 
`include "timescale.v"
`include "timescale.v"
 
 
module eth_cop
module eth_cop
(
(
  // WISHBONE common
  // WISHBONE common
Line 89... Line 88...
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
        s2_wb_dat_o
        s2_wb_dat_o
);
);
 
 
parameter Tp=1;
parameter Tp=1;
 
parameter ETH_BASE     = 32'hd0000000;
 
parameter ETH_WIDTH    = 32'h800;
 
parameter MEMORY_BASE  = 32'h2000;
 
parameter MEMORY_WIDTH = 32'h10000;
 
 
// WISHBONE common
// WISHBONE common
input wb_clk_i, wb_rst_i;
input wb_clk_i, wb_rst_i;
 
 
// WISHBONE MASTER 1
// WISHBONE MASTER 1
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reg           m1_wb_err_o;
reg           m1_wb_err_o;
reg           m2_wb_err_o;
reg           m2_wb_err_o;
 
 
wire m_wb_access_finished;
wire m_wb_access_finished;
wire m1_addressed_s1 = (m1_wb_adr_i >= `ETH_BASE) &
wire m1_addressed_s1 = (m1_wb_adr_i >= ETH_BASE) &
                       (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH));
                       (m1_wb_adr_i < (ETH_BASE + ETH_WIDTH));
wire m1_addressed_s2 = (m1_wb_adr_i >= `MEMORY_BASE) &
wire m1_addressed_s2 = (m1_wb_adr_i >= MEMORY_BASE) &
                       (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH));
                       (m1_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
wire m2_addressed_s1 = (m2_wb_adr_i >= `ETH_BASE) &
wire m2_addressed_s1 = (m2_wb_adr_i >= ETH_BASE) &
                       (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH));
                       (m2_wb_adr_i < (ETH_BASE + ETH_WIDTH));
wire m2_addressed_s2 = (m2_wb_adr_i >= `MEMORY_BASE) &
wire m2_addressed_s2 = (m2_wb_adr_i >= MEMORY_BASE) &
                       (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH));
                       (m2_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
 
 
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2);
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2);
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
always @ (posedge wb_clk_i or posedge wb_rst_i)

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