URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Diff between revs 346 and 352

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 346	Rev 352
Line 63...	Line 63...

`parameter DATA_WIDTH = 32;`	`parameter DATA_WIDTH = 32;`
`parameter DEPTH = 8;`	`parameter DEPTH = 8;`
`parameter CNT_WIDTH = 4;`	`parameter CNT_WIDTH = 4;`

`parameter Tp = 1;`

`input clk;`	`input clk;`
`input reset;`	`input reset;`
`input write;`	`input write;`
`input read;`	`input read;`
`input clear;`	`input clear;`
Line 96...	Line 94...


`always @ (posedge clk or posedge reset)`	`always @ (posedge clk or posedge reset)`
`begin`	`begin`
`if(reset)`	`if(reset)`
`cnt <=#Tp 0;`	`cnt <= 0;`
`else`	`else`
`if(clear)`	`if(clear)`
`cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};`	`cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};`
`else`	`else`
`if(read ^ write)`	`if(read ^ write)`
`if(read)`	`if(read)`
`cnt <=#Tp cnt - 1'b1;`	`cnt <= cnt - 1'b1;`
`else`	`else`
`cnt <=#Tp cnt + 1'b1;`	`cnt <= cnt + 1'b1;`
`end`	`end`

`always @ (posedge clk or posedge reset)`	`always @ (posedge clk or posedge reset)`
`begin`	`begin`
`if(reset)`	`if(reset)`
`read_pointer <=#Tp 0;`	`read_pointer <= 0;`
`else`	`else`
`if(clear)`	`if(clear)`
`read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};`	`read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};`
`else`	`else`
`if(read & ~empty)`	`if(read & ~empty)`
`read_pointer <=#Tp read_pointer + 1'b1;`	`read_pointer <= read_pointer + 1'b1;`
`end`	`end`

`always @ (posedge clk or posedge reset)`	`always @ (posedge clk or posedge reset)`
`begin`	`begin`
`if(reset)`	`if(reset)`
`write_pointer <=#Tp 0;`	`write_pointer <= 0;`
`else`	`else`
`if(clear)`	`if(clear)`
`write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};`	`write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};`
`else`	`else`
`if(write & ~full)`	`if(write & ~full)`
`write_pointer <=#Tp write_pointer + 1'b1;`	`write_pointer <= write_pointer + 1'b1;`
`end`	`end`

`assign empty = ~(\|cnt);`	`assign empty = ~(\|cnt);`
`assign almost_empty = cnt == 1;`	`assign almost_empty = cnt == 1;`
`assign full = cnt == DEPTH;`	`assign full = cnt == DEPTH;`
Line 163...	Line 161...
`); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE`	`); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE`
`else // !ETH_ALTERA_ALTSYNCRAM	`else // !ETH_ALTERA_ALTSYNCRAM
`always @ (posedge clk)`	`always @ (posedge clk)`
`begin`	`begin`
`if(write & clear)`	`if(write & clear)`
`fifo[0] <=#Tp data_in;`	`fifo[0] <= data_in;`
`else`	`else`
`if(write & ~full)`	`if(write & ~full)`
`fifo[write_pointer] <=#Tp data_in;`	`fifo[write_pointer] <= data_in;`
`end`	`end`


`always @ (posedge clk)`	`always @ (posedge clk)`
`begin`	`begin`
`if(clear)`	`if(clear)`
`data_out <=#Tp fifo[0];`	`data_out <= fifo[0];`
`else`	`else`
`data_out <=#Tp fifo[read_pointer];`	`data_out <= fifo[read_pointer];`
`end`	`end`
`endif // !ETH_ALTERA_ALTSYNCRAM	`endif // !ETH_ALTERA_ALTSYNCRAM
`endif // !ETH_FIFO_XILINX	`endif // !ETH_FIFO_XILINX

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Diff between revs 346 and 352