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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_fifo.v] - Diff between revs 352 and 354

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Rev 352 Rev 354
Line 57... Line 57...
//
//
 
 
`include "eth_defines.v"
`include "eth_defines.v"
`include "timescale.v"
`include "timescale.v"
 
 
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
 
                 almost_full, full, almost_empty, empty, cnt);
 
 
parameter DATA_WIDTH    = 32;
parameter DATA_WIDTH    = 32;
parameter DEPTH         = 8;
parameter DEPTH         = 8;
parameter CNT_WIDTH     = 4;
parameter CNT_WIDTH     = 4;
 
 
Line 106... Line 107...
      cnt <= cnt - 1'b1;
      cnt <= cnt - 1'b1;
    else
    else
      cnt <= cnt + 1'b1;
      cnt <= cnt + 1'b1;
end
end
 
 
 
 
always @ (posedge clk or posedge reset)
always @ (posedge clk or posedge reset)
begin
begin
  if(reset)
  if(reset)
    read_pointer <= 0;
    read_pointer <= 0;
  else
  else

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