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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.5 2002/11/21 00:14:39 mohor
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// Revision 1.5 2002/11/21 00:14:39 mohor
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// TxDone and TxAbort changed so they're not propagated to the wishbone
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// TxDone and TxAbort changed so they're not propagated to the wishbone
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// module when control frame is transmitted.
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// module when control frame is transmitted.
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//
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//
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// Revision 1.4 2002/11/19 17:37:32 mohor
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// Revision 1.4 2002/11/19 17:37:32 mohor
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module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
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module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
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TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
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TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
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ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
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ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
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MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
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MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
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TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
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TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
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ReceivedPauseFrm, ControlFrmAddressOK, LoadRxStatus, SetPauseTimer
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ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input TxFlow; // Tx flow control (from registers)
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input TxFlow; // Tx flow control (from registers)
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input RxFlow; // Rx flow control (from registers)
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input RxFlow; // Rx flow control (from registers)
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input DlyCrcEn; // Delayed CRC enabled (from registers)
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input DlyCrcEn; // Delayed CRC enabled (from registers)
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input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
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input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
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input [47:0] MAC; // MAC address (from registers)
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input [47:0] MAC; // MAC address (from registers)
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input LoadRxStatus;
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input RxStatusWriteLatched_sync2;
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input r_PassAll;
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output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
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output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
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output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
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output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
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output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
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output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
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output TxDoneOut; // Transmit packet done (to host)
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output TxDoneOut; // Transmit packet done (to host)
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Line 251... |
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
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.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
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.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
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.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
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.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
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.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
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.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
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.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
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.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
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.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
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.LoadRxStatus(LoadRxStatus), .SetPauseTimer(SetPauseTimer)
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.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
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);
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);
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eth_transmitcontrol transmitcontrol1
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eth_transmitcontrol transmitcontrol1
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(
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(
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