OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_maccontrol.v] - Diff between revs 349 and 352

Show entire file | Details | Blame | View Log

Rev 349 Rev 352
Line 92... Line 92...
                       TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
                       TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
                       ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
                       ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
                      );
                      );
 
 
 
 
parameter   Tp = 1;
 
 
 
 
 
input         MTxClk;                   // Transmit clock (from PHY)
input         MTxClk;                   // Transmit clock (from PHY)
input         MRxClk;                   // Receive clock (from PHY)
input         MRxClk;                   // Receive clock (from PHY)
input         TxReset;                  // Transmit reset
input         TxReset;                  // Transmit reset
input         RxReset;                  // Receive reset
input         RxReset;                  // Receive reset
Line 155... Line 153...
 
 
// Signal TxUsedDataOut was detected (a transfer is already in progress)
// Signal TxUsedDataOut was detected (a transfer is already in progress)
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    TxUsedDataOutDetected <= #Tp 1'b0;
    TxUsedDataOutDetected <=  1'b0;
  else
  else
  if(TxDoneIn | TxAbortIn)
  if(TxDoneIn | TxAbortIn)
    TxUsedDataOutDetected <= #Tp 1'b0;
    TxUsedDataOutDetected <=  1'b0;
  else
  else
  if(TxUsedDataOut)
  if(TxUsedDataOut)
    TxUsedDataOutDetected <= #Tp 1'b1;
    TxUsedDataOutDetected <=  1'b1;
end
end
 
 
 
 
// Latching variables
// Latching variables
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    begin
    begin
      TxAbortInLatched <= #Tp 1'b0;
      TxAbortInLatched <=  1'b0;
      TxDoneInLatched  <= #Tp 1'b0;
      TxDoneInLatched  <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      TxAbortInLatched <= #Tp TxAbortIn;
      TxAbortInLatched <=  TxAbortIn;
      TxDoneInLatched  <= #Tp TxDoneIn;
      TxDoneInLatched  <=  TxDoneIn;
    end
    end
end
end
 
 
 
 
 
 
// Generating muxed abort signal
// Generating muxed abort signal
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    MuxedAbort <= #Tp 1'b0;
    MuxedAbort <=  1'b0;
  else
  else
  if(TxStartFrmIn)
  if(TxStartFrmIn)
    MuxedAbort <= #Tp 1'b0;
    MuxedAbort <=  1'b0;
  else
  else
  if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
  if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
    MuxedAbort <= #Tp 1'b1;
    MuxedAbort <=  1'b1;
end
end
 
 
 
 
// Generating muxed done signal
// Generating muxed done signal
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    MuxedDone <= #Tp 1'b0;
    MuxedDone <=  1'b0;
  else
  else
  if(TxStartFrmIn)
  if(TxStartFrmIn)
    MuxedDone <= #Tp 1'b0;
    MuxedDone <=  1'b0;
  else
  else
  if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
  if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
    MuxedDone <= #Tp 1'b1;
    MuxedDone <=  1'b1;
end
end
 
 
 
 
// TxDoneOut
// TxDoneOut
assign TxDoneOut  = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
assign TxDoneOut  = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
Line 243... Line 241...
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
 
 
 
 
 
 
// Connecting receivecontrol module
// Connecting receivecontrol module
eth_receivecontrol #(.Tp(Tp))
eth_receivecontrol receivecontrol1
receivecontrol1
 
(
(
 .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
 .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
 .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
 .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
 .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
 .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
 .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
 .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
Line 256... Line 253...
 .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
 .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
 .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
 .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
);
);
 
 
 
 
eth_transmitcontrol #(.Tp(Tp))
eth_transmitcontrol transmitcontrol1
transmitcontrol1
 
(
(
 .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
 .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
 .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
 .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
 .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
 .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
 .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
 .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.