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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2005/02/21 12:48:07 igorm
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// Warning fixes.
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//
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// Revision 1.5 2003/05/16 10:08:27 mohor
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// Revision 1.5 2003/05/16 10:08:27 mohor
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// Busy was set 2 cycles too late. Reported by Dennis Scott.
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// Busy was set 2 cycles too late. Reported by Dennis Scott.
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//
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//
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// Revision 1.4 2002/08/14 18:32:10 mohor
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// Revision 1.4 2002/08/14 18:32:10 mohor
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// - Busy signal was not set on time when scan status operation was performed
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// - Busy signal was not set on time when scan status operation was performed
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Line 174... |
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reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
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reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
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reg [6:0] BitCounter; // Bit Counter
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reg [6:0] BitCounter; // Bit Counter
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wire MdcFrame; // Frame window for limiting the Mdc
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wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
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wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
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wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
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wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
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wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
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wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
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wire MdcEn_n;
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wire MdcEn_n;
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