OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_outputcontrol.v] - Diff between revs 346 and 352

Show entire file | Details | Blame | View Log

Rev 346 Rev 352
Line 68... Line 68...
 
 
`include "timescale.v"
`include "timescale.v"
 
 
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
 
 
parameter Tp = 1;
 
 
 
input         Clk;                // Host Clock
input         Clk;                // Host Clock
input         Reset;              // General Reset
input         Reset;              // General Reset
input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
input         NoPre;              // No Preamble (no 32-bit preamble)
input         NoPre;              // No Preamble (no 32-bit preamble)
input         InProgress;         // Operation in progress
input         InProgress;         // Operation in progress
Line 104... Line 102...
// Generation of the MdoEn signal
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      MdoEn_2d <= #Tp 1'b0;
      MdoEn_2d <=  1'b0;
      MdoEn_d <= #Tp 1'b0;
      MdoEn_d <=  1'b0;
      MdoEn <= #Tp 1'b0;
      MdoEn <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      if(MdcEn_n)
      if(MdcEn_n)
        begin
        begin
          MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
          MdoEn_2d <=  SerialEn | InProgress & BitCounter<32;
          MdoEn_d <= #Tp MdoEn_2d;
          MdoEn_d <=  MdoEn_2d;
          MdoEn <= #Tp MdoEn_d;
          MdoEn <=  MdoEn_d;
        end
        end
    end
    end
end
end
 
 
 
 
// Generation of the Mdo signal.
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      Mdo_2d <= #Tp 1'b0;
      Mdo_2d <=  1'b0;
      Mdo_d <= #Tp 1'b0;
      Mdo_d <=  1'b0;
      Mdo <= #Tp 1'b0;
      Mdo <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      if(MdcEn_n)
      if(MdcEn_n)
        begin
        begin
          Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
          Mdo_2d <=  ~SerialEn & BitCounter<32;
          Mdo_d <= #Tp ShiftedBit | Mdo_2d;
          Mdo_d <=  ShiftedBit | Mdo_2d;
          Mdo <= #Tp Mdo_d;
          Mdo <=  Mdo_d;
        end
        end
    end
    end
end
end
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.