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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_random.v] - Diff between revs 22 and 37

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
////                                                              ////
////  eth_random.v                                                ////
////  eth_random.v                                                ////
////                                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2001/10/19 08:43:51  mohor
 
// eth_timescale.v changed to timescale.v This is done because of the
 
// simulation of the few cores in a one joined project.
 
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// File eth_timescale.v is used to define timescale

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