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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_register.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 92... Line 92...
 
 
 
 
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    DataOut<=#1 RESET_VALUE;
    DataOut<= RESET_VALUE;
  else
  else
  if(SyncReset)
  if(SyncReset)
    DataOut<=#1 RESET_VALUE;
    DataOut<= RESET_VALUE;
  else
  else
  if(Write)                         // write
  if(Write)                         // write
    DataOut<=#1 DataIn;
    DataOut<= DataIn;
end
end
 
 
 
 
 
 
endmodule   // Register
endmodule   // Register

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