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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.2 2001/10/19 08:43:51 mohor
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// Revision 1.2 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module eth_register(DataIn, DataOut, Write, Clk, Reset, Default);
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module eth_register(DataIn, DataOut, Write, Clk, Reset);
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parameter WIDTH = 8; // default parameter of the register width
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parameter WIDTH = 8; // default parameter of the register width
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parameter ResetValue = 0;
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input [WIDTH-1:0] DataIn;
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input [WIDTH-1:0] DataIn;
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input Write;
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input Write;
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input Clk;
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input Clk;
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input Reset;
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input Reset;
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input [WIDTH-1:0] Default;
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output [WIDTH-1:0] DataOut;
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output [WIDTH-1:0] DataOut;
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reg [WIDTH-1:0] DataOut;
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reg [WIDTH-1:0] DataOut;
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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DataOut<=#1 Default;
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DataOut<=#1 ResetValue;
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else
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else
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if(Write) // write
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if(Write) // write
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DataOut<=#1 DataIn;
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DataOut<=#1 DataIn;
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end
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end
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