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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 74 and 102

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Rev 74 Rev 102
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.13  2002/02/26 16:18:09  mohor
 
// Reset values are passed to registers through parameters
 
//
// Revision 1.12  2002/02/17 13:23:42  mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
// Define missmatch fixed.
// Define missmatch fixed.
//
//
// Revision 1.11  2002/02/16 14:03:44  mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
// Registered trimmed. Unused registers removed.
// Registered trimmed. Unused registers removed.
Line 448... Line 451...
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    irq_txb <= 1'b0;
    irq_txb <= 1'b0;
  else
  else
  if(TxB_IRQ & INT_MASKOut[0])
  if(TxB_IRQ)
    irq_txb <= #Tp 1'b1;
    irq_txb <= #Tp 1'b1;
  else
  else
  if(INT_SOURCE_Wr & DataIn[0])
  if(INT_SOURCE_Wr & DataIn[0])
    irq_txb <= #Tp 1'b0;
    irq_txb <= #Tp 1'b0;
end
end
Line 460... Line 463...
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    irq_txe <= 1'b0;
    irq_txe <= 1'b0;
  else
  else
  if(TxE_IRQ & INT_MASKOut[1])
  if(TxE_IRQ)
    irq_txe <= #Tp 1'b1;
    irq_txe <= #Tp 1'b1;
  else
  else
  if(INT_SOURCE_Wr & DataIn[1])
  if(INT_SOURCE_Wr & DataIn[1])
    irq_txe <= #Tp 1'b0;
    irq_txe <= #Tp 1'b0;
end
end
Line 472... Line 475...
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    irq_rxb <= 1'b0;
    irq_rxb <= 1'b0;
  else
  else
  if(RxB_IRQ & INT_MASKOut[2])
  if(RxB_IRQ)
    irq_rxb <= #Tp 1'b1;
    irq_rxb <= #Tp 1'b1;
  else
  else
  if(INT_SOURCE_Wr & DataIn[2])
  if(INT_SOURCE_Wr & DataIn[2])
    irq_rxb <= #Tp 1'b0;
    irq_rxb <= #Tp 1'b0;
end
end
Line 484... Line 487...
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    irq_rxe <= 1'b0;
    irq_rxe <= 1'b0;
  else
  else
  if(RxE_IRQ & INT_MASKOut[3])
  if(RxE_IRQ)
    irq_rxe <= #Tp 1'b1;
    irq_rxe <= #Tp 1'b1;
  else
  else
  if(INT_SOURCE_Wr & DataIn[3])
  if(INT_SOURCE_Wr & DataIn[3])
    irq_rxe <= #Tp 1'b0;
    irq_rxe <= #Tp 1'b0;
end
end
Line 496... Line 499...
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    irq_busy <= 1'b0;
    irq_busy <= 1'b0;
  else
  else
  if(Busy_IRQ & INT_MASKOut[4])
  if(Busy_IRQ)
    irq_busy <= #Tp 1'b1;
    irq_busy <= #Tp 1'b1;
  else
  else
  if(INT_SOURCE_Wr & DataIn[4])
  if(INT_SOURCE_Wr & DataIn[4])
    irq_busy <= #Tp 1'b0;
    irq_busy <= #Tp 1'b0;
end
end
Line 508... Line 511...
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    irq_txc <= 1'b0;
    irq_txc <= 1'b0;
  else
  else
  if(TxC_IRQ & INT_MASKOut[5])
  if(TxC_IRQ)
    irq_txc <= #Tp 1'b1;
    irq_txc <= #Tp 1'b1;
  else
  else
  if(INT_SOURCE_Wr & DataIn[5])
  if(INT_SOURCE_Wr & DataIn[5])
    irq_txc <= #Tp 1'b0;
    irq_txc <= #Tp 1'b0;
end
end
Line 520... Line 523...
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    irq_rxc <= 1'b0;
    irq_rxc <= 1'b0;
  else
  else
  if(RxC_IRQ & INT_MASKOut[6])
  if(RxC_IRQ)
    irq_rxc <= #Tp 1'b1;
    irq_rxc <= #Tp 1'b1;
  else
  else
  if(INT_SOURCE_Wr & DataIn[6])
  if(INT_SOURCE_Wr & DataIn[6])
    irq_rxc <= #Tp 1'b0;
    irq_rxc <= #Tp 1'b0;
end
end
 
 
// Generating interrupt signal
// Generating interrupt signal
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxe | irq_busy | irq_txc | irq_rxc;
assign int_o = irq_txb  & INT_MASKOut[0] |
 
               irq_txe  & INT_MASKOut[1] |
 
               irq_rxb  & INT_MASKOut[2] |
 
               irq_rxe  & INT_MASKOut[3] |
 
               irq_busy & INT_MASKOut[4] |
 
               irq_txc  & INT_MASKOut[5] |
 
               irq_rxc  & INT_MASKOut[6] ;
 
 
// For reading interrupt status
// For reading interrupt status
assign INT_SOURCEOut = {26'h0, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
assign INT_SOURCEOut = {26'h0, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
 
 
 
 

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