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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 102 and 132

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Rev 102 Rev 132
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.14  2002/04/22 14:03:44  mohor
 
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
 
// or not.
 
//
// Revision 1.13  2002/02/26 16:18:09  mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
// Reset values are passed to registers through parameters
// Reset values are passed to registers through parameters
//
//
// Revision 1.12  2002/02/17 13:23:42  mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
// Define missmatch fixed.
// Define missmatch fixed.
Line 322... Line 326...
eth_register #(32, `ETH_HASH0_DEF)       RXHASH0     (.DataIn(DataIn),       .DataOut(HASH0Out),           .Write(HASH0_Wr),      .Clk(Clk), .Reset(Reset));
eth_register #(32, `ETH_HASH0_DEF)       RXHASH0     (.DataIn(DataIn),       .DataOut(HASH0Out),           .Write(HASH0_Wr),      .Clk(Clk), .Reset(Reset));
eth_register #(32, `ETH_HASH1_DEF)       RXHASH1     (.DataIn(DataIn),       .DataOut(HASH1Out),           .Write(HASH1_Wr),      .Clk(Clk), .Reset(Reset));
eth_register #(32, `ETH_HASH1_DEF)       RXHASH1     (.DataIn(DataIn),       .DataOut(HASH1Out),           .Write(HASH1_Wr),      .Clk(Clk), .Reset(Reset));
 
 
 
 
reg LinkFailRegister;
reg LinkFailRegister;
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
 
reg ResetLinkFailRegister_q1;
 
reg ResetLinkFailRegister_q2;
 
 
 
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
 
      LinkFailRegister <= #Tp 0;
      LinkFailRegister <= #Tp 0;
      ResetLinkFailRegister_q1 <= #Tp 0;
 
      ResetLinkFailRegister_q2 <= #Tp 0;
 
    end
 
  else
  else
    begin
 
      ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister;
 
      ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1;
 
      if(LinkFail)
      if(LinkFail)
        LinkFailRegister <= #Tp 1;
        LinkFailRegister <= #Tp 1;
      if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2)
  else
        LinkFailRegister <= #Tp 0;
        LinkFailRegister <= #Tp 0;
    end
    end
end
 
 
 
 
 
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
          IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
          IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
          MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
          MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or

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