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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 139 and 140

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Rev 139 Rev 140
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.16  2002/08/16 22:14:22  mohor
 
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
 
// changed from bit position 10 to 9.
 
//
// Revision 1.15  2002/08/14 18:26:37  mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
//
//
// Revision 1.14  2002/04/22 14:03:44  mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
Line 460... Line 464...
 
 
// MIITX_DATA Register
// MIITX_DATA Register
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
  (
  (
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0])
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
   .Write     (MIITX_DATA_Wr),
   .Write     (MIITX_DATA_Wr),
   .Clk       (Clk),
   .Clk       (Clk),
   .Reset     (Reset),
   .Reset     (Reset),
   .SyncReset (0)
   .SyncReset (0)
  );
  );

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