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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// File eth_timescale.v is used to define timescale
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Line 74... |
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_DmaEn,
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_DmaEn,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn, Busy_IRQ, RxF_IRQ,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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RxB_IRQ, TxE_IRQ, TxB_IRQ, Busy_MASK, RxF_MASK, RxB_MASK, TxE_MASK,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
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TxB_MASK, r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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UpdateMIIRX_DATAReg, Prsd, r_RxBDAddress, RX_BD_ADR_Wr
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UpdateMIIRX_DATAReg, Prsd, r_RxBDAddress, RX_BD_ADR_Wr, int_o
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] DataIn;
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input [31:0] DataIn;
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Line 122... |
output r_Bro;
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output r_Bro;
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output r_NoPre;
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output r_NoPre;
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output r_TxEn;
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output r_TxEn;
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output r_RxEn;
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output r_RxEn;
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output Busy_IRQ;
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input TxB_IRQ;
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output RxF_IRQ;
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input TxE_IRQ;
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output RxB_IRQ;
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input RxB_IRQ;
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output TxE_IRQ;
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input RxF_IRQ;
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output TxB_IRQ;
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input Busy_IRQ;
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output Busy_MASK;
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output RxF_MASK;
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output RxB_MASK;
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output TxE_MASK;
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output TxB_MASK;
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output [6:0] r_IPGT;
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output [6:0] r_IPGT;
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output [6:0] r_IPGR1;
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output [6:0] r_IPGR1;
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| Line 163... |
Line 163... |
input NValid_stat;
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input NValid_stat;
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input Busy_stat;
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input Busy_stat;
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input LinkFail;
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input LinkFail;
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output [47:0] r_MAC;
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output [47:0] r_MAC;
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output [7:0] r_RxBDAddress;
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output [7:0] r_RxBDAddress;
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output RX_BD_ADR_Wr;
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output RX_BD_ADR_Wr;
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output int_o;
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reg irq_txb;
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reg irq_txe;
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reg irq_rxb;
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reg irq_rxf;
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reg irq_busy;
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wire Write = Cs & Rw;
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wire Write = Cs & Rw;
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wire Read = Cs & ~Rw;
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wire Read = Cs & ~Rw;
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wire MODER_Wr = (Address == `ETH_MODER_ADR) & Write;
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wire MODER_Wr = (Address == `ETH_MODER_ADR) & Write;
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Line 218... |
wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] RX_BD_ADROut;
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wire [31:0] RX_BD_ADROut;
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) INT_SOURCE (.DataIn(DataIn), .DataOut(INT_SOURCEOut), .Write(INT_SOURCE_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_SOURCE_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
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eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
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Line 332... |
assign r_Bro = MODEROut[3];
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assign r_Bro = MODEROut[3];
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assign r_NoPre = MODEROut[2];
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assign r_NoPre = MODEROut[2];
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assign r_TxEn = MODEROut[1];
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assign r_TxEn = MODEROut[1];
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assign r_RxEn = MODEROut[0];
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assign r_RxEn = MODEROut[0];
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assign Busy_IRQ = INT_SOURCEOut[4];
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assign RxF_IRQ = INT_SOURCEOut[3];
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assign RxB_IRQ = INT_SOURCEOut[2];
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assign TxE_IRQ = INT_SOURCEOut[1];
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assign TxB_IRQ = INT_SOURCEOut[0];
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assign Busy_MASK = INT_MASKOut[4];
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assign RxF_MASK = INT_MASKOut[3];
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assign RxB_MASK = INT_MASKOut[2];
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assign TxE_MASK = INT_MASKOut[1];
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assign TxB_MASK = INT_MASKOut[0];
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assign r_IPGT[6:0] = IPGTOut[6:0];
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assign r_IPGT[6:0] = IPGTOut[6:0];
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assign r_IPGR1[6:0] = IPGR1Out[6:0];
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assign r_IPGR1[6:0] = IPGR1Out[6:0];
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assign r_IPGR2[6:0] = IPGR2Out[6:0];
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assign r_IPGR2[6:0] = IPGR2Out[6:0];
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Line 375... |
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
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assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
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assign r_RxBDAddress[7:0] = RX_BD_ADROut[7:0];
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assign r_RxBDAddress[7:0] = RX_BD_ADROut[7:0];
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// Interrupt generation
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always @ (posedge Clk or posedge Reset)
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begin
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if(Reset)
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irq_txb <= 1'b0;
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else
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if(TxB_IRQ & INT_MASKOut[0])
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irq_txb <= #Tp 1'b1;
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else
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if(INT_SOURCE_Wr & DataIn[0])
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irq_txb <= #Tp 1'b0;
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end
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always @ (posedge Clk or posedge Reset)
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begin
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if(Reset)
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irq_txe <= 1'b0;
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else
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if(TxE_IRQ & INT_MASKOut[1])
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irq_txe <= #Tp 1'b1;
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else
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if(INT_SOURCE_Wr & DataIn[1])
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irq_txe <= #Tp 1'b0;
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end
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always @ (posedge Clk or posedge Reset)
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begin
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if(Reset)
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irq_rxb <= 1'b0;
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else
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if(RxB_IRQ & INT_MASKOut[2])
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irq_rxb <= #Tp 1'b1;
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else
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if(INT_SOURCE_Wr & DataIn[2])
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irq_rxb <= #Tp 1'b0;
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end
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always @ (posedge Clk or posedge Reset)
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begin
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if(Reset)
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irq_rxf <= 1'b0;
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else
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if(RxF_IRQ & INT_MASKOut[3])
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irq_rxf <= #Tp 1'b1;
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else
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if(INT_SOURCE_Wr & DataIn[3])
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irq_rxf <= #Tp 1'b0;
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end
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always @ (posedge Clk or posedge Reset)
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begin
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if(Reset)
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irq_busy <= 1'b0;
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else
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if(Busy_IRQ & INT_MASKOut[4])
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irq_busy <= #Tp 1'b1;
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else
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if(INT_SOURCE_Wr & DataIn[4])
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irq_busy <= #Tp 1'b0;
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end
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// Generating interrupt signal
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assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxf | irq_busy;
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// For reading interrupt status
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assign INT_SOURCEOut = {28'h0, irq_busy, irq_rxf, irq_rxb, irq_txe, irq_txb};
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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