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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 164 and 244

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.21  2002/09/10 10:35:23  mohor
 
// Ethernet debug registers removed.
 
//
// Revision 1.20  2002/09/04 18:40:25  mohor
// Revision 1.20  2002/09/04 18:40:25  mohor
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
// the control frames connected.
// the control frames connected.
//
//
// Revision 1.19  2002/08/19 16:01:40  mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
Line 135... Line 138...
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
                      r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
Line 172... Line 175...
output r_RecSmall;
output r_RecSmall;
output r_Pad;
output r_Pad;
output r_HugEn;
output r_HugEn;
output r_CrcEn;
output r_CrcEn;
output r_DlyCrcEn;
output r_DlyCrcEn;
output r_Rst;
 
output r_FullD;
output r_FullD;
output r_ExDfrEn;
output r_ExDfrEn;
output r_NoBckof;
output r_NoBckof;
output r_LoopBck;
output r_LoopBck;
output r_IFG;
output r_IFG;
Line 649... Line 651...
assign r_RecSmall         = MODEROut[16];
assign r_RecSmall         = MODEROut[16];
assign r_Pad              = MODEROut[15];
assign r_Pad              = MODEROut[15];
assign r_HugEn            = MODEROut[14];
assign r_HugEn            = MODEROut[14];
assign r_CrcEn            = MODEROut[13];
assign r_CrcEn            = MODEROut[13];
assign r_DlyCrcEn         = MODEROut[12];
assign r_DlyCrcEn         = MODEROut[12];
assign r_Rst              = MODEROut[11];
// assign r_Rst           = MODEROut[11];   This signal is not used any more
assign r_FullD            = MODEROut[10];
assign r_FullD            = MODEROut[10];
assign r_ExDfrEn          = MODEROut[9];
assign r_ExDfrEn          = MODEROut[9];
assign r_NoBckof          = MODEROut[8];
assign r_NoBckof          = MODEROut[8];
assign r_LoopBck          = MODEROut[7];
assign r_LoopBck          = MODEROut[7];
assign r_IFG              = MODEROut[6];
assign r_IFG              = MODEROut[6];

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