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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 253 and 261

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Rev 253 Rev 261
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.23  2002/11/19 18:13:49  mohor
 
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
 
//
// Revision 1.22  2002/11/14 18:37:20  mohor
// Revision 1.22  2002/11/14 18:37:20  mohor
// r_Rst signal does not reset any module any more and is removed from the design.
// r_Rst signal does not reset any module any more and is removed from the design.
//
//
// Revision 1.21  2002/09/10 10:35:23  mohor
// Revision 1.21  2002/09/10 10:35:23  mohor
// Ethernet debug registers removed.
// Ethernet debug registers removed.
Line 151... Line 154...
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
                      StartTxDone, TxClk, RxClk, ReceivedPauseFrm
                      StartTxDone, TxClk, RxClk, SetPauseTimer
                    );
                    );
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
input [31:0] DataIn;
input [31:0] DataIn;
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input        RstTxPauseRq;
input        RstTxPauseRq;
input        TxCtrlEndFrm;
input        TxCtrlEndFrm;
input        StartTxDone;
input        StartTxDone;
input        TxClk;
input        TxClk;
input        RxClk;
input        RxClk;
input        ReceivedPauseFrm;      // sinhroniziraj tale shit da bo delal interrupt. Pazi na PassAll bit
input        SetPauseTimer;
 
 
reg          irq_txb;
reg          irq_txb;
reg          irq_txe;
reg          irq_txe;
reg          irq_rxb;
reg          irq_rxb;
reg          irq_rxe;
reg          irq_rxe;
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reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
 
 
reg SetRxCIrq_rxclk;
reg SetRxCIrq_rxclk;
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
reg SetRxCIrq;
reg SetRxCIrq;
reg ResetRxCIrq_sync1, ResetRxCIrq_sync2;
reg ResetRxCIrq_sync1;
 
reg ResetRxCIrq_sync2;
 
reg ResetRxCIrq_sync3;
 
 
wire Write = Cs &  Rw;
wire Write = Cs &  Rw;
wire Read  = Cs & ~Rw;
wire Read  = Cs & ~Rw;
 
 
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
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always @ (posedge RxClk or posedge Reset)
always @ (posedge RxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    SetRxCIrq_rxclk <=#Tp 1'b0;
    SetRxCIrq_rxclk <=#Tp 1'b0;
  else
  else
  if(ReceivedPauseFrm & r_RxFlow)
  if(SetPauseTimer & r_RxFlow)
    SetRxCIrq_rxclk <=#Tp 1'b1;
    SetRxCIrq_rxclk <=#Tp 1'b1;
  else
  else
  if(ResetRxCIrq_sync2)
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
    SetRxCIrq_rxclk <=#Tp 1'b0;
    SetRxCIrq_rxclk <=#Tp 1'b0;
end
end
 
 
 
 
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
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    ResetRxCIrq_sync1 <=#Tp 1'b0;
    ResetRxCIrq_sync1 <=#Tp 1'b0;
  else
  else
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
end
end
 
 
always @ (posedge TxClk or posedge Reset)
always @ (posedge RxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ResetRxCIrq_sync2 <=#Tp 1'b0;
    ResetRxCIrq_sync2 <=#Tp 1'b0;
  else
  else
    ResetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
    ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
end
end
 
 
 
always @ (posedge RxClk or posedge Reset)
 
begin
 
  if(Reset)
 
    ResetRxCIrq_sync3 <=#Tp 1'b0;
 
  else
 
    ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
 
end
 
 
 
 
 
 
// Interrupt generation
// Interrupt generation
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)

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