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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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// added.
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//
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//
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Revision 1.2 2001/09/24 15:02:56 mohor
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| Line 85... |
Line 89... |
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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UpdateMIIRX_DATAReg, Prsd, r_RxBDAddress, RX_BD_ADR_Wr, int_o
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UpdateMIIRX_DATAReg, Prsd, r_RxBDNum, RX_BD_NUM_Wr, int_o
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] DataIn;
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input [31:0] DataIn;
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| Line 167... |
Line 171... |
input NValid_stat;
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input NValid_stat;
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input Busy_stat;
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input Busy_stat;
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input LinkFail;
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input LinkFail;
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output [47:0]r_MAC;
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output [47:0]r_MAC;
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output [7:0] r_RxBDAddress;
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output [7:0] r_RxBDNum;
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output RX_BD_ADR_Wr;
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output RX_BD_NUM_Wr;
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output int_o;
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output int_o;
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reg irq_txb;
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reg irq_txb;
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reg irq_txe;
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reg irq_txe;
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reg irq_rxb;
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reg irq_rxb;
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| Line 198... |
Line 202... |
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
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wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
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wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
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wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
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wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
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wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
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wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
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wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
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wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
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wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
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assign RX_BD_ADR_Wr = (Address == `ETH_RX_BD_ADR_ADR ) & Write;
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assign RX_BD_NUM_Wr = (Address == `ETH_RX_BD_NUM_ADR ) & Write;
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [31:0] INT_SOURCEOut;
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wire [31:0] INT_SOURCEOut;
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| Line 219... |
Line 223... |
wire [31:0] MIITX_DATAOut;
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wire [31:0] MIITX_DATAOut;
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wire [31:0] MIIRX_DATAOut;
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wire [31:0] MIIRX_DATAOut;
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wire [31:0] MIISTATUSOut;
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wire [31:0] MIISTATUSOut;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] RX_BD_ADROut;
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wire [31:0] RX_BD_NUMOut;
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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| Line 253... |
Line 257... |
eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
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eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
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//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF));
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//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF));
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eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
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eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
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eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
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eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
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assign RX_BD_ADROut[31:8] = 24'h0;
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assign RX_BD_NUMOut[31:8] = 24'h0;
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eth_register #(8) RX_BD_ADR (.DataIn(DataIn[7:0]), .DataOut(RX_BD_ADROut[7:0]), .Write(RX_BD_ADR_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_RX_BD_ADR_DEF));
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eth_register #(8) RX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(RX_BD_NUMOut[7:0]), .Write(RX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_RX_BD_NUM_DEF));
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reg LinkFailRegister;
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reg LinkFailRegister;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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reg ResetLinkFailRegister_q1;
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reg ResetLinkFailRegister_q1;
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| Line 286... |
Line 290... |
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always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
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always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
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IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
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IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
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MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
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MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
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MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
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MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
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RX_BD_ADROut)
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RX_BD_NUMOut)
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begin
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begin
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if(Read) // read
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if(Read) // read
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begin
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begin
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case(Address)
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case(Address)
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`ETH_MODER_ADR : DataOut<=MODEROut;
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`ETH_MODER_ADR : DataOut<=MODEROut;
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| Line 308... |
Line 312... |
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
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`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
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`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
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`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
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`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
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`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
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`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
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`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
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`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
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`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
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`ETH_RX_BD_ADR_ADR : DataOut<=RX_BD_ADROut;
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`ETH_RX_BD_NUM_ADR : DataOut<=RX_BD_NUMOut;
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default: DataOut<=32'h0;
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default: DataOut<=32'h0;
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endcase
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endcase
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end
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end
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else
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else
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DataOut<=32'h0;
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DataOut<=32'h0;
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| Line 376... |
Line 380... |
assign MIISTATUSOut[0] = LinkFailRegister ;
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assign MIISTATUSOut[0] = LinkFailRegister ;
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assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
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assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
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assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
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assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
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assign r_RxBDAddress[7:0] = RX_BD_ADROut[7:0];
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assign r_RxBDNum[7:0] = RX_BD_NUMOut[7:0];
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// Interrupt generation
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// Interrupt generation
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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