Line 176... |
Line 176... |
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
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r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
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r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
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dbg_dat,
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StartTxDone, TxClk, RxClk, SetPauseTimer
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StartTxDone, TxClk, RxClk, SetPauseTimer
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);
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);
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|
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input [31:0] DataIn;
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input [31:0] DataIn;
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input [7:0] Address;
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input [7:0] Address;
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Line 266... |
Line 267... |
input StartTxDone;
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input StartTxDone;
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input TxClk;
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input TxClk;
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input RxClk;
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input RxClk;
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input SetPauseTimer;
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input SetPauseTimer;
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|
|
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input [31:0] dbg_dat; // debug data input
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|
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reg irq_txb;
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reg irq_txb;
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reg irq_txe;
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reg irq_txe;
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reg irq_rxb;
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reg irq_rxb;
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reg irq_rxe;
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reg irq_rxe;
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reg irq_busy;
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reg irq_busy;
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Line 309... |
Line 312... |
wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
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wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
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wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
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wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
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wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
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wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
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wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
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wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
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wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
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wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
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wire DBG_REG_Sel = (Address == `ETH_DBG_ADR );
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wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
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wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
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|
|
|
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wire [2:0] MODER_Wr;
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wire [2:0] MODER_Wr;
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wire [0:0] INT_SOURCE_Wr;
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wire [0:0] INT_SOURCE_Wr;
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Line 400... |
Line 404... |
wire [31:0] MAC_ADDR1Out;
|
wire [31:0] MAC_ADDR1Out;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] HASH0Out;
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wire [31:0] HASH0Out;
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wire [31:0] HASH1Out;
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wire [31:0] HASH1Out;
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wire [31:0] TXCTRLOut;
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wire [31:0] TXCTRLOut;
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wire [31:0] DBGOut;
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|
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// MODER Register
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// MODER Register
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eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
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eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
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(
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(
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.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
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.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
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Line 869... |
Line 874... |
`ETH_MAC_ADDR1_ADR : DataOut=MAC_ADDR1Out;
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`ETH_MAC_ADDR1_ADR : DataOut=MAC_ADDR1Out;
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`ETH_TX_BD_NUM_ADR : DataOut=TX_BD_NUMOut;
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`ETH_TX_BD_NUM_ADR : DataOut=TX_BD_NUMOut;
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`ETH_HASH0_ADR : DataOut=HASH0Out;
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`ETH_HASH0_ADR : DataOut=HASH0Out;
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`ETH_HASH1_ADR : DataOut=HASH1Out;
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`ETH_HASH1_ADR : DataOut=HASH1Out;
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`ETH_TX_CTRL_ADR : DataOut=TXCTRLOut;
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`ETH_TX_CTRL_ADR : DataOut=TXCTRLOut;
|
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`ETH_DBG_ADR : DataOut=dbg_dat;
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default: DataOut=32'h0;
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default: DataOut=32'h0;
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endcase
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endcase
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end
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end
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else
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else
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DataOut=32'h0;
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DataOut=32'h0;
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