| Line 140... |
Line 140... |
output r_Iam;
|
output r_Iam;
|
output r_Bro;
|
output r_Bro;
|
output r_NoPre;
|
output r_NoPre;
|
output r_TxEn;
|
output r_TxEn;
|
output r_RxEn;
|
output r_RxEn;
|
|
output [31:0] r_HASH0;
|
|
output [31:0] r_HASH1;
|
|
|
input TxB_IRQ;
|
input TxB_IRQ;
|
input TxE_IRQ;
|
input TxE_IRQ;
|
input RxB_IRQ;
|
input RxB_IRQ;
|
input RxF_IRQ;
|
input RxF_IRQ;
|
| Line 176... |
Line 178... |
output [4:0] r_RGAD;
|
output [4:0] r_RGAD;
|
output [4:0] r_FIAD;
|
output [4:0] r_FIAD;
|
|
|
output [15:0]r_CtrlData;
|
output [15:0]r_CtrlData;
|
|
|
output [31:0]r_HASH0;
|
|
output [31:0]r_HASH1;
|
|
|
|
|
|
input NValid_stat;
|
input NValid_stat;
|
input Busy_stat;
|
input Busy_stat;
|
input LinkFail;
|
input LinkFail;
|
|
|
| Line 216... |
Line 215... |
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
|
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
|
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
|
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
|
wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
|
wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
|
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
|
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
|
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
|
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
|
|
wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
|
|
wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
|
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write;
|
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write;
|
wire MAC_HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
|
|
wire MAC_HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
|
|
|
|
|
|
|
|
wire [31:0] MODEROut;
|
wire [31:0] MODEROut;
|
wire [31:0] INT_SOURCEOut;
|
wire [31:0] INT_SOURCEOut;
|
| Line 240... |
Line 239... |
wire [31:0] MIIRX_DATAOut;
|
wire [31:0] MIIRX_DATAOut;
|
wire [31:0] MIISTATUSOut;
|
wire [31:0] MIISTATUSOut;
|
wire [31:0] MAC_ADDR0Out;
|
wire [31:0] MAC_ADDR0Out;
|
wire [31:0] MAC_ADDR1Out;
|
wire [31:0] MAC_ADDR1Out;
|
wire [31:0] TX_BD_NUMOut;
|
wire [31:0] TX_BD_NUMOut;
|
wire [31:0] MAC_HASH0Out;
|
wire [31:0] HASH0Out;
|
wire [31:0] MAC_HASH1Out;
|
wire [31:0] HASH1Out;
|
|
|
|
|
|
|
eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
|
eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
|
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
|
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
|
eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
|
eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
|
eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
|
eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
|
eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
|
eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
|
eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
|
eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
|
eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF));
|
eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF));
|
|
eth_register #(32) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
|
|
eth_register #(32) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
|
|
|
|
|
|
|
// CTRLMODER registers
|
// CTRLMODER registers
|
wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF;
|
wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF;
|
assign CTRLMODEROut[31:3] = 29'h0;
|
assign CTRLMODEROut[31:3] = 29'h0;
|
eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
|
eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
|
| Line 279... |
Line 283... |
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
|
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
|
|
|
assign TX_BD_NUMOut[31:8] = 24'h0;
|
assign TX_BD_NUMOut[31:8] = 24'h0;
|
eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
|
eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
|
|
|
eth_register #(32) MAC_HASH0 (.DataIn(DataIn), .DataOut(MAC_HASH0Out), .Write(MAC_HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
|
|
eth_register #(32) MAC_HASH1 (.DataIn(DataIn), .DataOut(MAC_HASH1Out), .Write(MAC_HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
|
|
|
|
|
|
reg LinkFailRegister;
|
reg LinkFailRegister;
|
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
|
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
|
reg ResetLinkFailRegister_q1;
|
reg ResetLinkFailRegister_q1;
|
reg ResetLinkFailRegister_q2;
|
reg ResetLinkFailRegister_q2;
|
| Line 312... |
Line 313... |
|
|
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
|
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
|
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
|
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
|
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
|
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
|
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
|
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
|
TX_BD_NUMOut or MAC_HASH0Out or MAC_HASH1Out)
|
TX_BD_NUMOut or HASH0Out or HASH1Out)
|
begin
|
begin
|
if(Read) // read
|
if(Read) // read
|
begin
|
begin
|
case(Address)
|
case(Address)
|
`ETH_MODER_ADR : DataOut<=MODEROut;
|
`ETH_MODER_ADR : DataOut<=MODEROut;
|
| Line 335... |
Line 336... |
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
|
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
|
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
|
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
|
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
|
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
|
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
|
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
|
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
|
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
|
`ETH_HASH0_ADR : DataOut<=MAC_HASH0Out;
|
`ETH_HASH0_ADR : DataOut<=HASH0Out;
|
`ETH_HASH1_ADR : DataOut<=MAC_HASH1Out;
|
`ETH_HASH1_ADR : DataOut<=HASH1Out;
|
default: DataOut<=32'h0;
|
default: DataOut<=32'h0;
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
DataOut<=32'h0;
|
DataOut<=32'h0;
|
| Line 403... |
Line 404... |
assign MIISTATUSOut[1] = 1'b0;
|
assign MIISTATUSOut[1] = 1'b0;
|
assign MIISTATUSOut[0] = LinkFailRegister ;
|
assign MIISTATUSOut[0] = LinkFailRegister ;
|
|
|
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
|
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
|
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
|
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
|
|
assign r_HASH1[31:0] = HASH1Out;
|
|
assign r_HASH0[31:0] = HASH0Out;
|
|
|
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
|
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
|
|
|
assign r_HASH0 = MAC_HASH0Out;
|
|
assign r_HASH1 = MAC_HASH1Out;
|
|
|
|
// Interrupt generation
|
// Interrupt generation
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
