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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2002/02/15 11:08:25 mohor
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// File format fixed a bit.
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//
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// Revision 1.9 2002/02/14 20:19:41 billditt
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// Revision 1.9 2002/02/14 20:19:41 billditt
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// Modified for Address Checking,
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// Modified for Address Checking,
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// addition of eth_addrcheck.v
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// addition of eth_addrcheck.v
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//
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//
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// Revision 1.8 2002/02/12 17:01:19 mohor
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// Revision 1.8 2002/02/12 17:01:19 mohor
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_DmaEn,
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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input [15:0] Prsd;
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input [15:0] Prsd;
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output [31:0] DataOut;
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output [31:0] DataOut;
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reg [31:0] DataOut;
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reg [31:0] DataOut;
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output r_DmaEn;
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output r_RecSmall;
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output r_RecSmall;
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output r_Pad;
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output r_Pad;
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output r_HugEn;
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output r_HugEn;
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output r_CrcEn;
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output r_CrcEn;
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output r_DlyCrcEn;
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output r_DlyCrcEn;
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wire [31:0] HASH0Out;
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wire [31:0] HASH0Out;
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wire [31:0] HASH1Out;
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wire [31:0] HASH1Out;
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(17) MODER (.DataIn(DataIn[16:0]), .DataOut(MODEROut[16:0]), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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assign MODEROut[31:17] = 0;
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
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eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF));
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eth_register #(32) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
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eth_register #(32) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
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eth_register #(5) INT_MASK (.DataIn(DataIn[4:0]), .DataOut(INT_MASKOut[4:0]), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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assign INT_MASKOut[31:5] = 0;
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eth_register #(7) IPGT (.DataIn(DataIn[6:0]), .DataOut(IPGTOut[6:0]), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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assign IPGTOut[31:7] = 0;
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// CTRLMODER registers
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eth_register #(7) IPGR1 (.DataIn(DataIn[6:0]), .DataOut(IPGR1Out[6:0]), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF;
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assign IPGR1Out[31:7] = 0;
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assign CTRLMODEROut[31:3] = 29'h0;
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eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
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// End: CTRLMODER registers
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eth_register #(7) IPGR2 (.DataIn(DataIn[6:0]), .DataOut(IPGR2Out[6:0]), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
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assign IPGR2Out[31:7] = 0;
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
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eth_register #(6) COLLCONF0 (.DataIn(DataIn[5:0]), .DataOut(COLLCONFOut[5:0]), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF0_DEF));
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eth_register #(4) COLLCONF1 (.DataIn(DataIn[19:16]),.DataOut(COLLCONFOut[19:16]), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF1_DEF));
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assign COLLCONFOut[15:6] = 0;
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assign COLLCONFOut[31:20] = 0;
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eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
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assign TX_BD_NUMOut[31:8] = 24'h0;
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eth_register #(32) MIIMODER (.DataIn(DataIn), .DataOut(MIIMODEROut), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
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eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_CTRLMODER_DEF));
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assign CTRLMODEROut[31:3] = 29'h0;
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eth_register #(11) MIIMODER (.DataIn(DataIn[10:0]), .DataOut(MIIMODEROut[10:0]), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
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assign MIIMODEROut[31:11] = 0;
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assign MIICOMMANDOut[31:3] = 29'h0;
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eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
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eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
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eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
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eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
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eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
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eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
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assign MIICOMMANDOut[31:3] = 29'h0;
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eth_register #(5) MIIADDRESS0 (.DataIn(DataIn[4:0]), .DataOut(MIIADDRESSOut[4:0]), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF0));
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eth_register #(5) MIIADDRESS1 (.DataIn(DataIn[12:8]), .DataOut(MIIADDRESSOut[12:8]),.Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF1));
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assign MIIADDRESSOut[7:5] = 0;
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assign MIIADDRESSOut[31:13] = 0;
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eth_register #(16) MIITX_DATA (.DataIn(DataIn[15:0]), .DataOut(MIITX_DATAOut[15:0]),.Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
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assign MIITX_DATAOut[31:16] = 0;
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eth_register #(16) MIIRX_DATA (.DataIn(Prsd[15:0]), .DataOut(MIIRX_DATAOut[15:0]),.Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
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assign MIIRX_DATAOut[31:16] = 0;
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eth_register #(32) MIIADDRESS (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF));
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eth_register #(32) MIITX_DATA (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
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eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
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//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF));
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eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
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eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
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eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
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eth_register #(16) MAC_ADDR1 (.DataIn(DataIn[15:0]), .DataOut(MAC_ADDR1Out[15:0]), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
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assign MAC_ADDR1Out[31:16] = 0;
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assign TX_BD_NUMOut[31:8] = 24'h0;
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eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
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eth_register #(32) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
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eth_register #(32) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
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reg LinkFailRegister;
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reg LinkFailRegister;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
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reg ResetLinkFailRegister_q1;
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reg ResetLinkFailRegister_q1;
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else
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else
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DataOut<=32'h0;
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DataOut<=32'h0;
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end
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end
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assign r_DmaEn = MODEROut[17];
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assign r_RecSmall = MODEROut[16];
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assign r_RecSmall = MODEROut[16];
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assign r_Pad = MODEROut[15];
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assign r_Pad = MODEROut[15];
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assign r_HugEn = MODEROut[14];
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assign r_HugEn = MODEROut[14];
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assign r_CrcEn = MODEROut[13];
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assign r_CrcEn = MODEROut[13];
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assign r_DlyCrcEn = MODEROut[12];
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assign r_DlyCrcEn = MODEROut[12];
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Line 421... |
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
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assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
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assign MIISTATUSOut[31:10] = 22'h0 ;
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assign MIISTATUSOut[31:10] = 22'h0 ;
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assign MIISTATUSOut[9] = NValid_stat ;
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assign MIISTATUSOut[9] = NValid_stat ;
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assign MIISTATUSOut[8] = Busy_stat ;
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assign MIISTATUSOut[8] = Busy_stat ;
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assign MIISTATUSOut[7:3]= 5'h0 ;
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assign MIISTATUSOut[7:1]= 7'h0 ;
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assign MIISTATUSOut[2] = 1'b0;
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assign MIISTATUSOut[1] = 1'b0;
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assign MIISTATUSOut[0] = LinkFailRegister ;
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assign MIISTATUSOut[0] = LinkFailRegister ;
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assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
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assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
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assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
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assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
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assign r_HASH1[31:0] = HASH1Out;
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assign r_HASH1[31:0] = HASH1Out;
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