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//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
////  eth_registers.v                                             ////
 
////  eth_registers.v                                             ////
 
////                                                              ////
 
////                                                              ////
 
////  This file is part of the Ethernet IP core project           ////
 
////  This file is part of the Ethernet IP core project           ////
 
////  http://www.opencores.org/projects/ethmac/                   ////
 
////  http://www.opencores.org/projects/ethmac/                   ////
 
////                                                              ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////  Author(s):                                                  ////
 
////      - Igor Mohor (igorM@opencores.org)                      ////
 
////      - Igor Mohor (igorM@opencores.org)                      ////
 
////                                                              ////
 
////                                                              ////
 
////  All additional information is avaliable in the Readme.txt   ////
 
////  All additional information is avaliable in the Readme.txt   ////
 
////  file.                                                       ////
 
////  file.                                                       ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
//// Copyright (C) 2001 Authors                                   ////
 
//// Copyright (C) 2001 Authors                                   ////
 
////                                                              ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
//// later version.                                               ////
 
////                                                              ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
//// details.                                                     ////
 
////                                                              ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.10  2002/02/15 11:08:25  mohor
 
 
 
// File format fixed a bit.
 
 
 
//
 
// Revision 1.9  2002/02/14 20:19:41  billditt
 
// Revision 1.9  2002/02/14 20:19:41  billditt
 
// Modified for Address Checking,
 
// Modified for Address Checking,
 
// addition of eth_addrcheck.v
 
// addition of eth_addrcheck.v
 
//
 
//
 
// Revision 1.8  2002/02/12 17:01:19  mohor
 
// Revision 1.8  2002/02/12 17:01:19  mohor
 
// HASH0 and HASH1 registers added. 
// HASH0 and HASH1 registers added. 
 
 
 
 
// Revision 1.7  2002/01/23 10:28:16  mohor
 
// Revision 1.7  2002/01/23 10:28:16  mohor
 
// Link in the header changed.
 
// Link in the header changed.
 
//
 
//
 
// Revision 1.6  2001/12/05 15:00:16  mohor
 
// Revision 1.6  2001/12/05 15:00:16  mohor
 
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
 
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
 
// instead of the number of RX descriptors).
 
// instead of the number of RX descriptors).
 
//
 
//
 
// Revision 1.5  2001/12/05 10:22:19  mohor
 
// Revision 1.5  2001/12/05 10:22:19  mohor
 
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
 
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
 
//
 
//
 
// Revision 1.4  2001/10/19 08:43:51  mohor
 
// Revision 1.4  2001/10/19 08:43:51  mohor
 
// eth_timescale.v changed to timescale.v This is done because of the
 
// eth_timescale.v changed to timescale.v This is done because of the
 
// simulation of the few cores in a one joined project.
 
// simulation of the few cores in a one joined project.
 
//
 
//
 
// Revision 1.3  2001/10/18 12:07:11  mohor
 
// Revision 1.3  2001/10/18 12:07:11  mohor
 
// Status signals changed, Adress decoding changed, interrupt controller
 
// Status signals changed, Adress decoding changed, interrupt controller
 
// added.
 
// added.
 
//
 
//
 
// Revision 1.2  2001/09/24 15:02:56  mohor
 
// Revision 1.2  2001/09/24 15:02:56  mohor
 
// Defines changed (All precede with ETH_). Small changes because some
 
// Defines changed (All precede with ETH_). Small changes because some
 
// tools generate warnings when two operands are together. Synchronization
 
// tools generate warnings when two operands are together. Synchronization
 
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
 
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
 
// demands).
 
// demands).
 
//
 
//
 
// Revision 1.1  2001/08/06 14:44:29  mohor
 
// Revision 1.1  2001/08/06 14:44:29  mohor
 
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
 
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
 
// Include files fixed to contain no path.
 
// Include files fixed to contain no path.
 
// File names and module names changed ta have a eth_ prologue in the name.
 
// File names and module names changed ta have a eth_ prologue in the name.
 
// File eth_timescale.v is used to define timescale
 
// File eth_timescale.v is used to define timescale
 
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
 
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
 
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
 
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
 
// and Mdo_OE. The bidirectional signal must be created on the top level. This
 
// and Mdo_OE. The bidirectional signal must be created on the top level. This
 
// is done due to the ASIC tools.
 
// is done due to the ASIC tools.
 
//
 
//
 
// Revision 1.2  2001/08/02 09:25:31  mohor
 
// Revision 1.2  2001/08/02 09:25:31  mohor
 
// Unconnected signals are now connected.
 
// Unconnected signals are now connected.
 
//
 
//
 
// Revision 1.1  2001/07/30 21:23:42  mohor
 
// Revision 1.1  2001/07/30 21:23:42  mohor
 
// Directory structure changed. Files checked and joind together.
 
// Directory structure changed. Files checked and joind together.
 
//
 
//
 
//
 
//
 
//
 
//
 
//
 
//
 
//
 
//
 
//
 
//
 
 
 
 
 
`include "eth_defines.v"
 
`include "eth_defines.v"
 
`include "timescale.v"
 
`include "timescale.v"
 
 
 
 
 
 
 
 
 
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_DmaEn,
 
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
 
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
 
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
 
                      r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
 
                      r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
 
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
 
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
 
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
 
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
 
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
 
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
 
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
 
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
 
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
 
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
 
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
 
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
 
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
 
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
 
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
 
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
 
                      r_HASH0, r_HASH1
 
                      r_HASH0, r_HASH1
 
                    );
 
                    );
 
 
 
 
 
parameter Tp = 1;
 
parameter Tp = 1;
 
 
 
 
 
input [31:0] DataIn;
 
input [31:0] DataIn;
 
input [7:0] Address;
 
input [7:0] Address;
 
 
 
 
 
input Rw;
 
input Rw;
 
input Cs;
 
input Cs;
 
input Clk;
 
input Clk;
 
input Reset;
 
input Reset;
 
 
 
 
 
input WCtrlDataStart;
 
input WCtrlDataStart;
 
input RStatStart;
 
input RStatStart;
 
 
 
 
 
input UpdateMIIRX_DATAReg;
 
input UpdateMIIRX_DATAReg;
 
input [15:0] Prsd;
 
input [15:0] Prsd;
 
 
 
 
 
output [31:0] DataOut;
 
output [31:0] DataOut;
 
reg    [31:0] DataOut;
 
reg    [31:0] DataOut;
 
 
 
 
 
output r_DmaEn;
 
 
 
output r_RecSmall;
 
output r_RecSmall;
 
output r_Pad;
 
output r_Pad;
 
output r_HugEn;
 
output r_HugEn;
 
output r_CrcEn;
 
output r_CrcEn;
 
output r_DlyCrcEn;
 
output r_DlyCrcEn;
 
output r_Rst;
 
output r_Rst;
 
output r_FullD;
 
output r_FullD;
 
output r_ExDfrEn;
 
output r_ExDfrEn;
 
output r_NoBckof;
 
output r_NoBckof;
 
output r_LoopBck;
 
output r_LoopBck;
 
output r_IFG;
 
output r_IFG;
 
output r_Pro;
 
output r_Pro;
 
output r_Iam;
 
output r_Iam;
 
output r_Bro;
 
output r_Bro;
 
output r_NoPre;
 
output r_NoPre;
 
output r_TxEn;
 
output r_TxEn;
 
output r_RxEn;
 
output r_RxEn;
 
output [31:0] r_HASH0;
 
output [31:0] r_HASH0;
 
output [31:0] r_HASH1;
 
output [31:0] r_HASH1;
 
 
 
 
 
input TxB_IRQ;
 
input TxB_IRQ;
 
input TxE_IRQ;
 
input TxE_IRQ;
 
input RxB_IRQ;
 
input RxB_IRQ;
 
input RxF_IRQ;
 
input RxF_IRQ;
 
input Busy_IRQ;
 
input Busy_IRQ;
 
 
 
 
 
output [6:0] r_IPGT;
 
output [6:0] r_IPGT;
 
 
 
 
 
output [6:0] r_IPGR1;
 
output [6:0] r_IPGR1;
 
 
 
 
 
output [6:0] r_IPGR2;
 
output [6:0] r_IPGR2;
 
 
 
 
 
output [15:0] r_MinFL;
 
output [15:0] r_MinFL;
 
output [15:0] r_MaxFL;
 
output [15:0] r_MaxFL;
 
 
 
 
 
output [3:0] r_MaxRet;
 
output [3:0] r_MaxRet;
 
output [5:0] r_CollValid;
 
output [5:0] r_CollValid;
 
 
 
 
 
output r_TxFlow;
 
output r_TxFlow;
 
output r_RxFlow;
 
output r_RxFlow;
 
output r_PassAll;
 
output r_PassAll;
 
 
 
 
 
output r_MiiMRst;
 
output r_MiiMRst;
 
output r_MiiNoPre;
 
output r_MiiNoPre;
 
output [7:0] r_ClkDiv;
 
output [7:0] r_ClkDiv;
 
 
 
 
 
output r_WCtrlData;
 
output r_WCtrlData;
 
output r_RStat;
 
output r_RStat;
 
output r_ScanStat;
 
output r_ScanStat;
 
 
 
 
 
output [4:0] r_RGAD;
 
output [4:0] r_RGAD;
 
output [4:0] r_FIAD;
 
output [4:0] r_FIAD;
 
 
 
 
 
output [15:0]r_CtrlData;
 
output [15:0]r_CtrlData;
 
 
 
 
 
 
 
 
 
input NValid_stat;
 
input NValid_stat;
 
input Busy_stat;
 
input Busy_stat;
 
input LinkFail;
 
input LinkFail;
 
 
 
 
 
output [47:0]r_MAC;
 
output [47:0]r_MAC;
 
output [7:0] r_TxBDNum;
 
output [7:0] r_TxBDNum;
 
output       TX_BD_NUM_Wr;
 
output       TX_BD_NUM_Wr;
 
output       int_o;
 
output       int_o;
 
 
 
 
 
reg          irq_txb;
 
reg          irq_txb;
 
reg          irq_txe;
 
reg          irq_txe;
 
reg          irq_rxb;
 
reg          irq_rxb;
 
reg          irq_rxf;
 
reg          irq_rxf;
 
reg          irq_busy;
 
reg          irq_busy;
 
 
 
 
 
wire Write = Cs &  Rw;
 
wire Write = Cs &  Rw;
 
wire Read  = Cs & ~Rw;
 
wire Read  = Cs & ~Rw;
 
 
 
 
 
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
 
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
 
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
 
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
 
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
 
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
 
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
 
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
 
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
 
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
 
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
 
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
 
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
 
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
 
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
 
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
 
 
 
 
 
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
 
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
 
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
 
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
 
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
 
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
 
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
 
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
 
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
 
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
 
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
 
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
 
wire MIISTATUS_Wr   = (Address == `ETH_MIISTATUS_ADR   )  & Write;
 
wire MIISTATUS_Wr   = (Address == `ETH_MIISTATUS_ADR   )  & Write;
 
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
 
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
 
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
 
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
 
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR   )  & Write;
 
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR   )  & Write;
 
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR   )  & Write;
 
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR   )  & Write;
 
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write;
 
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write;
 
 
 
 
 
 
 
 
 
 
 
 
 
wire [31:0] MODEROut;
 
wire [31:0] MODEROut;
 
wire [31:0] INT_SOURCEOut;
 
wire [31:0] INT_SOURCEOut;
 
wire [31:0] INT_MASKOut;
 
wire [31:0] INT_MASKOut;
 
wire [31:0] IPGTOut;
 
wire [31:0] IPGTOut;
 
wire [31:0] IPGR1Out;
 
wire [31:0] IPGR1Out;
 
wire [31:0] IPGR2Out;
 
wire [31:0] IPGR2Out;
 
wire [31:0] PACKETLENOut;
 
wire [31:0] PACKETLENOut;
 
wire [31:0] COLLCONFOut;
 
wire [31:0] COLLCONFOut;
 
wire [31:0] CTRLMODEROut;
 
wire [31:0] CTRLMODEROut;
 
wire [31:0] MIIMODEROut;
 
wire [31:0] MIIMODEROut;
 
wire [31:0] MIICOMMANDOut;
 
wire [31:0] MIICOMMANDOut;
 
wire [31:0] MIIADDRESSOut;
 
wire [31:0] MIIADDRESSOut;
 
wire [31:0] MIITX_DATAOut;
 
wire [31:0] MIITX_DATAOut;
 
wire [31:0] MIIRX_DATAOut;
 
wire [31:0] MIIRX_DATAOut;
 
wire [31:0] MIISTATUSOut;
 
wire [31:0] MIISTATUSOut;
 
wire [31:0] MAC_ADDR0Out;
 
wire [31:0] MAC_ADDR0Out;
 
wire [31:0] MAC_ADDR1Out;
 
wire [31:0] MAC_ADDR1Out;
 
wire [31:0] TX_BD_NUMOut;
 
wire [31:0] TX_BD_NUMOut;
 
wire [31:0] HASH0Out;
 
wire [31:0] HASH0Out;
 
wire [31:0] HASH1Out;
 
wire [31:0] HASH1Out;
 
 
 
 
 
 
 
 
 
 
 
 
 
eth_register #(32) MODER       (.DataIn(DataIn), .DataOut(MODEROut),      .Write(MODER_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
 
eth_register #(17) MODER       (.DataIn(DataIn[16:0]), .DataOut(MODEROut[16:0]),     .Write(MODER_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
 
eth_register #(32) INT_MASK    (.DataIn(DataIn), .DataOut(INT_MASKOut),   .Write(INT_MASK_Wr),   .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
 
assign MODEROut[31:17] = 0;
 
eth_register #(32) IPGT        (.DataIn(DataIn), .DataOut(IPGTOut),       .Write(IPGT_Wr),       .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
 
 
 
eth_register #(32) IPGR1       (.DataIn(DataIn), .DataOut(IPGR1Out),      .Write(IPGR1_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
 
 
 
eth_register #(32) IPGR2       (.DataIn(DataIn), .DataOut(IPGR2Out),      .Write(IPGR2_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
 
 
 
eth_register #(32) PACKETLEN   (.DataIn(DataIn), .DataOut(PACKETLENOut),  .Write(PACKETLEN_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
 
 
 
eth_register #(32) COLLCONF    (.DataIn(DataIn), .DataOut(COLLCONFOut),   .Write(COLLCONF_Wr),   .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF));
 
 
 
eth_register #(32) RXHASH0     (.DataIn(DataIn), .DataOut(HASH0Out),      .Write(HASH0_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
 
 
 
eth_register #(32) RXHASH1     (.DataIn(DataIn), .DataOut(HASH1Out),      .Write(HASH1_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
 
 
 
 
 
 
 
 
 
eth_register #(5) INT_MASK     (.DataIn(DataIn[4:0]),  .DataOut(INT_MASKOut[4:0]),   .Write(INT_MASK_Wr),   .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
 
 
 
assign INT_MASKOut[31:5] = 0;
 
 
 
 
 
 
 
eth_register #(7)  IPGT        (.DataIn(DataIn[6:0]),  .DataOut(IPGTOut[6:0]),       .Write(IPGT_Wr),       .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
 
 
 
assign IPGTOut[31:7] = 0;
 
 
 
 
 
// CTRLMODER registers
 
eth_register #(7)  IPGR1       (.DataIn(DataIn[6:0]),  .DataOut(IPGR1Out[6:0]),      .Write(IPGR1_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
 
wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF;
 
assign IPGR1Out[31:7] = 0;
 
assign CTRLMODEROut[31:3] = 29'h0;
 
 
 
eth_register #(3)  CTRLMODER2  (.DataIn(DataIn[2:0]),   .DataOut(CTRLMODEROut[2:0]),   .Write(CTRLMODER_Wr),  .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
 
 
 
// End: CTRLMODER registers
 
 
 
 
 
 
 
 
 
eth_register #(7)  IPGR2       (.DataIn(DataIn[6:0]),  .DataOut(IPGR2Out[6:0]),      .Write(IPGR2_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
 
 
 
assign IPGR2Out[31:7] = 0;
 
 
 
 
 
 
 
eth_register #(32) PACKETLEN   (.DataIn(DataIn),       .DataOut(PACKETLENOut),       .Write(PACKETLEN_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
 
 
 
 
 
 
 
eth_register #(6) COLLCONF0    (.DataIn(DataIn[5:0]),  .DataOut(COLLCONFOut[5:0]),   .Write(COLLCONF_Wr),   .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF0_DEF));
 
 
 
eth_register #(4) COLLCONF1    (.DataIn(DataIn[19:16]),.DataOut(COLLCONFOut[19:16]), .Write(COLLCONF_Wr),   .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF1_DEF));
 
 
 
assign COLLCONFOut[15:6] = 0;
 
 
 
assign COLLCONFOut[31:20] = 0;
 
 
 
 
 
 
 
eth_register #(8) TX_BD_NUM    (.DataIn(DataIn[7:0]),  .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
 
 
 
assign TX_BD_NUMOut[31:8] = 24'h0;
 
 
 
 
 
eth_register #(32) MIIMODER    (.DataIn(DataIn), .DataOut(MIIMODEROut),   .Write(MIIMODER_Wr),   .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
 
eth_register #(3)  CTRLMODER2  (.DataIn(DataIn[2:0]),  .DataOut(CTRLMODEROut[2:0]),  .Write(CTRLMODER_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_CTRLMODER_DEF));
 
 
 
assign CTRLMODEROut[31:3] = 29'h0;
 
 
 
 
 
 
 
eth_register #(11) MIIMODER    (.DataIn(DataIn[10:0]), .DataOut(MIIMODEROut[10:0]),  .Write(MIIMODER_Wr),   .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
 
 
 
assign MIIMODEROut[31:11] = 0;
 
 
 
 
 
assign MIICOMMANDOut[31:3] = 29'h0;
 
 
 
eth_register #(1) MIICOMMAND2  (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
 
eth_register #(1) MIICOMMAND2  (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
 
eth_register #(1) MIICOMMAND1  (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
 
eth_register #(1)  MIICOMMAND1 (.DataIn(DataIn[1]),    .DataOut(MIICOMMANDOut[1]),   .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart),     .Default(1'b0));
 
eth_register #(1) MIICOMMAND0  (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
 
eth_register #(1) MIICOMMAND0  (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
 
 
 
assign MIICOMMANDOut[31:3] = 29'h0;
 
 
 
 
 
 
 
eth_register #(5)  MIIADDRESS0 (.DataIn(DataIn[4:0]),  .DataOut(MIIADDRESSOut[4:0]), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF0));
 
 
 
eth_register #(5)  MIIADDRESS1 (.DataIn(DataIn[12:8]), .DataOut(MIIADDRESSOut[12:8]),.Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF1));
 
 
 
assign MIIADDRESSOut[7:5] = 0;
 
 
 
assign MIIADDRESSOut[31:13] = 0;
 
 
 
 
 
 
 
eth_register #(16) MIITX_DATA  (.DataIn(DataIn[15:0]), .DataOut(MIITX_DATAOut[15:0]),.Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
 
 
 
assign MIITX_DATAOut[31:16] = 0;
 
 
 
 
 
 
 
eth_register #(16) MIIRX_DATA  (.DataIn(Prsd[15:0]),   .DataOut(MIIRX_DATAOut[15:0]),.Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
 
 
 
assign MIIRX_DATAOut[31:16] = 0;
 
 
 
 
 
eth_register #(32) MIIADDRESS  (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF));
 
 
 
eth_register #(32) MIITX_DATA  (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
 
 
 
eth_register #(32) MIIRX_DATA  (.DataIn({16'h0, Prsd}),   .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
 
 
 
//eth_register #(32) MIISTATUS   (.DataIn(DataIn), .DataOut(MIISTATUSOut),  .Write(MIISTATUS_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF));
 
 
 
eth_register #(32) MAC_ADDR0   (.DataIn(DataIn), .DataOut(MAC_ADDR0Out),  .Write(MAC_ADDR0_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
 
eth_register #(32) MAC_ADDR0   (.DataIn(DataIn), .DataOut(MAC_ADDR0Out),  .Write(MAC_ADDR0_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
 
eth_register #(32) MAC_ADDR1   (.DataIn(DataIn), .DataOut(MAC_ADDR1Out),  .Write(MAC_ADDR1_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
 
eth_register #(16) MAC_ADDR1   (.DataIn(DataIn[15:0]), .DataOut(MAC_ADDR1Out[15:0]), .Write(MAC_ADDR1_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
 
 
 
assign MAC_ADDR1Out[31:16] = 0;
 
 
 
 
 
assign TX_BD_NUMOut[31:8] = 24'h0;
 
 
 
eth_register #(8) TX_BD_NUM   (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr),  .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
 
eth_register #(32) RXHASH0     (.DataIn(DataIn),       .DataOut(HASH0Out),           .Write(HASH0_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
 
 
 
eth_register #(32) RXHASH1     (.DataIn(DataIn),       .DataOut(HASH1Out),           .Write(HASH1_Wr),      .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
 
 
 
 
 
 
 
 
 
reg LinkFailRegister;
 
reg LinkFailRegister;
 
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
 
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
 
reg ResetLinkFailRegister_q1;
 
reg ResetLinkFailRegister_q1;
 
reg ResetLinkFailRegister_q2;
 
reg ResetLinkFailRegister_q2;
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    begin
 
    begin
 
      LinkFailRegister <= #Tp 0;
 
      LinkFailRegister <= #Tp 0;
 
      ResetLinkFailRegister_q1 <= #Tp 0;
 
      ResetLinkFailRegister_q1 <= #Tp 0;
 
      ResetLinkFailRegister_q2 <= #Tp 0;
 
      ResetLinkFailRegister_q2 <= #Tp 0;
 
    end
 
    end
 
  else
 
  else
 
    begin
 
    begin
 
      ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister;
 
      ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister;
 
      ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1;
 
      ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1;
 
      if(LinkFail)
 
      if(LinkFail)
 
        LinkFailRegister <= #Tp 1;
 
        LinkFailRegister <= #Tp 1;
 
      if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2)
 
      if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2)
 
        LinkFailRegister <= #Tp 0;
 
        LinkFailRegister <= #Tp 0;
 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 
 
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
 
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
 
          IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
 
          IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
 
          MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
 
          MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
 
          MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
 
          MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
 
          TX_BD_NUMOut or HASH0Out or HASH1Out)
 
          TX_BD_NUMOut or HASH0Out or HASH1Out)
 
begin
 
begin
 
  if(Read)  // read
 
  if(Read)  // read
 
    begin
 
    begin
 
      case(Address)
 
      case(Address)
 
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
 
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
 
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
 
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
 
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
 
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
 
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
 
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
 
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
 
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
 
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
 
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
 
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
 
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
 
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
 
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
 
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
 
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
 
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
 
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
 
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
 
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
 
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
 
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
 
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
 
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
 
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
 
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
 
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
 
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
 
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
 
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
 
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
 
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
 
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
 
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
 
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
 
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
 
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
 
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
 
        default:             DataOut<=32'h0;
 
        default:             DataOut<=32'h0;
 
      endcase
 
      endcase
 
    end
 
    end
 
  else
 
  else
 
    DataOut<=32'h0;
 
    DataOut<=32'h0;
 
end
 
end
 
 
 
 
 
 
 
 
 
assign r_DmaEn            = MODEROut[17];
 
 
 
assign r_RecSmall         = MODEROut[16];
 
assign r_RecSmall         = MODEROut[16];
 
assign r_Pad              = MODEROut[15];
 
assign r_Pad              = MODEROut[15];
 
assign r_HugEn            = MODEROut[14];
 
assign r_HugEn            = MODEROut[14];
 
assign r_CrcEn            = MODEROut[13];
 
assign r_CrcEn            = MODEROut[13];
 
assign r_DlyCrcEn         = MODEROut[12];
 
assign r_DlyCrcEn         = MODEROut[12];
 
assign r_Rst              = MODEROut[11];
 
assign r_Rst              = MODEROut[11];
 
assign r_FullD            = MODEROut[10];
 
assign r_FullD            = MODEROut[10];
 
assign r_ExDfrEn          = MODEROut[9];
 
assign r_ExDfrEn          = MODEROut[9];
 
assign r_NoBckof          = MODEROut[8];
 
assign r_NoBckof          = MODEROut[8];
 
assign r_LoopBck          = MODEROut[7];
 
assign r_LoopBck          = MODEROut[7];
 
assign r_IFG              = MODEROut[6];
 
assign r_IFG              = MODEROut[6];
 
assign r_Pro              = MODEROut[5];
 
assign r_Pro              = MODEROut[5];
 
assign r_Iam              = MODEROut[4];
 
assign r_Iam              = MODEROut[4];
 
assign r_Bro              = MODEROut[3];
 
assign r_Bro              = MODEROut[3];
 
assign r_NoPre            = MODEROut[2];
 
assign r_NoPre            = MODEROut[2];
 
assign r_TxEn             = MODEROut[1];
 
assign r_TxEn             = MODEROut[1];
 
assign r_RxEn             = MODEROut[0];
 
assign r_RxEn             = MODEROut[0];
 
 
 
 
 
assign r_IPGT[6:0]        = IPGTOut[6:0];
 
assign r_IPGT[6:0]        = IPGTOut[6:0];
 
 
 
 
 
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
 
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
 
 
 
 
 
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
 
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
 
 
 
 
 
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
 
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
 
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
 
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
 
 
 
 
 
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
 
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
 
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
 
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
 
 
 
 
 
assign r_TxFlow           = CTRLMODEROut[2];
 
assign r_TxFlow           = CTRLMODEROut[2];
 
assign r_RxFlow           = CTRLMODEROut[1];
 
assign r_RxFlow           = CTRLMODEROut[1];
 
assign r_PassAll          = CTRLMODEROut[0];
 
assign r_PassAll          = CTRLMODEROut[0];
 
 
 
 
 
assign r_MiiMRst          = MIIMODEROut[10];
 
assign r_MiiMRst          = MIIMODEROut[10];
 
assign r_MiiNoPre         = MIIMODEROut[8];
 
assign r_MiiNoPre         = MIIMODEROut[8];
 
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
 
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
 
 
 
 
 
assign r_WCtrlData        = MIICOMMANDOut[2];
 
assign r_WCtrlData        = MIICOMMANDOut[2];
 
assign r_RStat            = MIICOMMANDOut[1];
 
assign r_RStat            = MIICOMMANDOut[1];
 
assign r_ScanStat         = MIICOMMANDOut[0];
 
assign r_ScanStat         = MIICOMMANDOut[0];
 
 
 
 
 
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
 
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
 
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
 
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
 
 
 
 
 
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
 
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
 
 
 
 
 
assign MIISTATUSOut[31:10] = 22'h0           ;
 
assign MIISTATUSOut[31:10] = 22'h0           ;
 
assign MIISTATUSOut[9]  = NValid_stat        ;
 
assign MIISTATUSOut[9]  = NValid_stat        ;
 
assign MIISTATUSOut[8]  = Busy_stat          ;
 
assign MIISTATUSOut[8]  = Busy_stat          ;
 
assign MIISTATUSOut[7:3]= 5'h0               ;
 
assign MIISTATUSOut[7:1]= 7'h0               ;
 
assign MIISTATUSOut[2]  = 1'b0;
 
 
 
assign MIISTATUSOut[1]  = 1'b0;
 
 
 
assign MIISTATUSOut[0]  = LinkFailRegister   ;
 
assign MIISTATUSOut[0]  = LinkFailRegister   ;
 
 
 
 
 
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
 
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
 
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
 
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
 
assign r_HASH1[31:0]      = HASH1Out;
 
assign r_HASH1[31:0]      = HASH1Out;
 
assign r_HASH0[31:0]      = HASH0Out;
 
assign r_HASH0[31:0]      = HASH0Out;
 
 
 
 
 
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
 
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
 
 
 
 
 
 
 
 
 
// Interrupt generation
 
// Interrupt generation
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_txb <= 1'b0;
 
    irq_txb <= 1'b0;
 
  else
 
  else
 
  if(TxB_IRQ & INT_MASKOut[0])
 
  if(TxB_IRQ & INT_MASKOut[0])
 
    irq_txb <= #Tp 1'b1;
 
    irq_txb <= #Tp 1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr & DataIn[0])
 
  if(INT_SOURCE_Wr & DataIn[0])
 
    irq_txb <= #Tp 1'b0;
 
    irq_txb <= #Tp 1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_txe <= 1'b0;
 
    irq_txe <= 1'b0;
 
  else
 
  else
 
  if(TxE_IRQ & INT_MASKOut[1])
 
  if(TxE_IRQ & INT_MASKOut[1])
 
    irq_txe <= #Tp 1'b1;
 
    irq_txe <= #Tp 1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr & DataIn[1])
 
  if(INT_SOURCE_Wr & DataIn[1])
 
    irq_txe <= #Tp 1'b0;
 
    irq_txe <= #Tp 1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_rxb <= 1'b0;
 
    irq_rxb <= 1'b0;
 
  else
 
  else
 
  if(RxB_IRQ & INT_MASKOut[2])
 
  if(RxB_IRQ & INT_MASKOut[2])
 
    irq_rxb <= #Tp 1'b1;
 
    irq_rxb <= #Tp 1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr & DataIn[2])
 
  if(INT_SOURCE_Wr & DataIn[2])
 
    irq_rxb <= #Tp 1'b0;
 
    irq_rxb <= #Tp 1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_rxf <= 1'b0;
 
    irq_rxf <= 1'b0;
 
  else
 
  else
 
  if(RxF_IRQ & INT_MASKOut[3])
 
  if(RxF_IRQ & INT_MASKOut[3])
 
    irq_rxf <= #Tp 1'b1;
 
    irq_rxf <= #Tp 1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr & DataIn[3])
 
  if(INT_SOURCE_Wr & DataIn[3])
 
    irq_rxf <= #Tp 1'b0;
 
    irq_rxf <= #Tp 1'b0;
 
end
 
end
 
 
 
 
 
always @ (posedge Clk or posedge Reset)
 
always @ (posedge Clk or posedge Reset)
 
begin
 
begin
 
  if(Reset)
 
  if(Reset)
 
    irq_busy <= 1'b0;
 
    irq_busy <= 1'b0;
 
  else
 
  else
 
  if(Busy_IRQ & INT_MASKOut[4])
 
  if(Busy_IRQ & INT_MASKOut[4])
 
    irq_busy <= #Tp 1'b1;
 
    irq_busy <= #Tp 1'b1;
 
  else
 
  else
 
  if(INT_SOURCE_Wr & DataIn[4])
 
  if(INT_SOURCE_Wr & DataIn[4])
 
    irq_busy <= #Tp 1'b0;
 
    irq_busy <= #Tp 1'b0;
 
end
 
end
 
 
 
 
 
// Generating interrupt signal
 
// Generating interrupt signal
 
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxf | irq_busy;
 
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxf | irq_busy;
 
 
 
 
 
// For reading interrupt status
 
// For reading interrupt status
 
assign INT_SOURCEOut = {28'h0, irq_busy, irq_rxf, irq_rxb, irq_txe, irq_txb};
 
assign INT_SOURCEOut = {28'h0, irq_busy, irq_rxf, irq_rxb, irq_txe, irq_txb};
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 

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