| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2004/04/26 15:26:23 igorm
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// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
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// previous update of the core.
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// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
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// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
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// register. (thanks to Mathias and Torbjorn)
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// - Multicast reception was fixed. Thanks to Ulrich Gries
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//
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// Revision 1.11 2004/03/17 09:32:15 igorm
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// Revision 1.11 2004/03/17 09:32:15 igorm
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// Multicast detection fixed. Only the LSB of the first byte is checked.
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// Multicast detection fixed. Only the LSB of the first byte is checked.
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//
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//
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// Revision 1.10 2002/11/22 01:57:06 mohor
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// Revision 1.10 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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| Line 150... |
Line 158... |
reg Broadcast;
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reg Broadcast;
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reg Multicast;
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reg Multicast;
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reg [5:0] CrcHash;
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reg [5:0] CrcHash;
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reg CrcHashGood;
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reg CrcHashGood;
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reg DelayData;
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reg DelayData;
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reg [3:0] LatchedNibble;
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reg [7:0] LatchedByte;
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reg [7:0] LatchedByte;
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reg [7:0] RxData_d;
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reg [7:0] RxData_d;
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reg RxValid_d;
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reg RxValid_d;
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reg RxStartFrm_d;
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reg RxStartFrm_d;
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reg RxEndFrm_d;
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reg RxEndFrm_d;
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| Line 177... |
Line 184... |
wire GenerateRxValid;
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wire GenerateRxValid;
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wire GenerateRxStartFrm;
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wire GenerateRxStartFrm;
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wire GenerateRxEndFrm;
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wire GenerateRxEndFrm;
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wire DribbleRxEndFrm;
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wire DribbleRxEndFrm;
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wire [3:0] DlyCrcCnt;
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wire [3:0] DlyCrcCnt;
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wire IFGCounterEq24;
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assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEq5 = MRxD == 4'h5;
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assign MRxDEq5 = MRxD == 4'h5;
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| Line 202... |
Line 209... |
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
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.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
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.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
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.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
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.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
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.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
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.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
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.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
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.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
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.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
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.ByteCnt(ByteCnt)
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.ByteCntOut(ByteCnt)
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);
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);
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// Rx Address Check
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// Rx Address Check
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eth_rxaddrcheck rxaddrcheck1
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eth_rxaddrcheck rxaddrcheck1
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| Line 260... |
Line 267... |
begin
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begin
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if(Reset)
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if(Reset)
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begin
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begin
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RxData_d[7:0] <= #Tp 8'h0;
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RxData_d[7:0] <= #Tp 8'h0;
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DelayData <= #Tp 1'b0;
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DelayData <= #Tp 1'b0;
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LatchedNibble[3:0] <= #Tp 4'h0;
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LatchedByte[7:0] <= #Tp 8'h0;
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LatchedByte[7:0] <= #Tp 8'h0;
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RxData[7:0] <= #Tp 8'h0;
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RxData[7:0] <= #Tp 8'h0;
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end
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end
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else
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else
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begin
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begin
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LatchedNibble[3:0] <= #Tp MRxD[3:0]; // Latched nibble
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LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
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LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedNibble[3:0]}; // Latched byte
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DelayData <= #Tp StateData[0];
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DelayData <= #Tp StateData[0];
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if(GenerateRxValid)
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if(GenerateRxValid)
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RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
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RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
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else
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else
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