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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxethmac.v] - Diff between revs 349 and 352

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Rev 349 Rev 352
Line 117... Line 117...
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
                    );
                    );
 
 
parameter Tp = 1;
 
 
 
 
 
 
 
input         MRxClk;
input         MRxClk;
input         MRxDV;
input         MRxDV;
input   [3:0] MRxD;
input   [3:0] MRxD;
Line 196... Line 194...
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
assign MRxDEq5 = MRxD == 4'h5;
 
 
 
 
// Rx State Machine module
// Rx State Machine module
eth_rxstatem #(.Tp(Tp))
eth_rxstatem
rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
                        .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
                        .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
                        .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
                        .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
                        .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
                        .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
                        .StateSFD(StateSFD), .StateDrop(StateDrop)
                        .StateSFD(StateSFD), .StateDrop(StateDrop)
                       );
                       );
 
 
 
 
// Rx Counters module
// Rx Counters module
eth_rxcounters #(.Tp(Tp))
eth_rxcounters
rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
                            .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
                            .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
                            .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
                            .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
                            .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
                            .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
                            .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
                            .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
Line 221... Line 219...
                            .ByteCntOut(ByteCnt)
                            .ByteCntOut(ByteCnt)
                           );
                           );
 
 
// Rx Address Check
// Rx Address Check
 
 
eth_rxaddrcheck #(.Tp(Tp))
eth_rxaddrcheck
rxaddrcheck1
rxaddrcheck1
              (.MRxClk(MRxClk),         .Reset( Reset),             .RxData(RxData),
              (.MRxClk(MRxClk),         .Reset( Reset),             .RxData(RxData),
               .Broadcast (Broadcast),  .r_Bro (r_Bro),             .r_Pro(r_Pro),
               .Broadcast (Broadcast),  .r_Bro (r_Bro),             .r_Pro(r_Pro),
               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),    .ByteCntEq2(ByteCntEq2),
               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),    .ByteCntEq2(ByteCntEq2),
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4),    .ByteCntEq5(ByteCntEq5),
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4),    .ByteCntEq5(ByteCntEq5),
Line 245... Line 243...
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
assign Data_Crc[3] = MRxD[0];
 
 
 
 
// Connecting module Crc
// Connecting module Crc
eth_crc #(.Tp(Tp))
eth_crc
crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
               .Crc(Crc), .CrcError(CrcError)
               .Crc(Crc), .CrcError(CrcError)
              );
              );
 
 
 
 
 
 
// Latching CRC for use in the hash table
// Latching CRC for use in the hash table
 
 
always @ (posedge MRxClk)
always @ (posedge MRxClk)
begin
begin
  CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
  CrcHashGood <=  StateData[0] & ByteCntEq6;
end
end
 
 
always @ (posedge MRxClk)
always @ (posedge MRxClk)
begin
begin
  if(Reset | StateIdle)
  if(Reset | StateIdle)
    CrcHash[5:0] <= #Tp 6'h0;
    CrcHash[5:0] <=  6'h0;
  else
  else
  if(StateData[0] & ByteCntEq6)
  if(StateData[0] & ByteCntEq6)
    CrcHash[5:0] <= #Tp Crc[31:26];
    CrcHash[5:0] <=  Crc[31:26];
end
end
 
 
 
 
// Output byte stream
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      RxData_d[7:0]      <= #Tp 8'h0;
      RxData_d[7:0]      <=  8'h0;
      DelayData          <= #Tp 1'b0;
      DelayData          <=  1'b0;
      LatchedByte[7:0]   <= #Tp 8'h0;
      LatchedByte[7:0]   <=  8'h0;
      RxData[7:0]        <= #Tp 8'h0;
      RxData[7:0]        <=  8'h0;
    end
    end
  else
  else
    begin
    begin
      LatchedByte[7:0]   <= #Tp {MRxD[3:0], LatchedByte[7:4]};  // Latched byte
      LatchedByte[7:0]   <=  {MRxD[3:0], LatchedByte[7:4]};  // Latched byte
      DelayData          <= #Tp StateData[0];
      DelayData          <=  StateData[0];
 
 
      if(GenerateRxValid)
      if(GenerateRxValid)
        RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}};  // Data goes through only in data state 
        RxData_d[7:0] <=  LatchedByte[7:0] & {8{|StateData}};  // Data goes through only in data state 
      else
      else
      if(~DelayData)
      if(~DelayData)
        RxData_d[7:0] <= #Tp 8'h0;                                // Delaying data to be valid for two cycles. Zero when not active.
        RxData_d[7:0] <=  8'h0;                                // Delaying data to be valid for two cycles. Zero when not active.
 
 
      RxData[7:0] <= #Tp RxData_d[7:0];                           // Output data byte
      RxData[7:0] <=  RxData_d[7:0];                           // Output data byte
    end
    end
end
end
 
 
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    Broadcast <= #Tp 1'b0;
    Broadcast <=  1'b0;
  else
  else
    begin
    begin
      if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
      if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
        Broadcast <= #Tp 1'b0;
        Broadcast <=  1'b0;
      else
      else
      if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
      if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
        Broadcast <= #Tp 1'b1;
        Broadcast <=  1'b1;
      else
      else
      if(RxAbort | RxEndFrm)
      if(RxAbort | RxEndFrm)
        Broadcast <= #Tp 1'b0;
        Broadcast <=  1'b0;
    end
    end
end
end
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    Multicast <= #Tp 1'b0;
    Multicast <=  1'b0;
  else
  else
    begin
    begin
      if(StateData[0] & ByteCntEq1 & LatchedByte[0])
      if(StateData[0] & ByteCntEq1 & LatchedByte[0])
        Multicast <= #Tp 1'b1;
        Multicast <=  1'b1;
      else if(RxAbort | RxEndFrm)
      else if(RxAbort | RxEndFrm)
      Multicast <= #Tp 1'b0;
      Multicast <=  1'b0;
    end
    end
end
end
 
 
 
 
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      RxValid_d <= #Tp 1'b0;
      RxValid_d <=  1'b0;
      RxValid   <= #Tp 1'b0;
      RxValid   <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      RxValid_d <= #Tp GenerateRxValid;
      RxValid_d <=  GenerateRxValid;
      RxValid   <= #Tp RxValid_d;
      RxValid   <=  RxValid_d;
    end
    end
end
end
 
 
 
 
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      RxStartFrm_d <= #Tp 1'b0;
      RxStartFrm_d <=  1'b0;
      RxStartFrm   <= #Tp 1'b0;
      RxStartFrm   <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      RxStartFrm_d <= #Tp GenerateRxStartFrm;
      RxStartFrm_d <=  GenerateRxStartFrm;
      RxStartFrm   <= #Tp RxStartFrm_d;
      RxStartFrm   <=  RxStartFrm_d;
    end
    end
end
end
 
 
 
 
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
Line 370... Line 368...
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      RxEndFrm_d <= #Tp 1'b0;
      RxEndFrm_d <=  1'b0;
      RxEndFrm   <= #Tp 1'b0;
      RxEndFrm   <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      RxEndFrm_d <= #Tp GenerateRxEndFrm;
      RxEndFrm_d <=  GenerateRxEndFrm;
      RxEndFrm   <= #Tp RxEndFrm_d | DribbleRxEndFrm;
      RxEndFrm   <=  RxEndFrm_d | DribbleRxEndFrm;
    end
    end
end
end
 
 
 
 
endmodule
endmodule

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