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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  eth_rxethmac.v                                              ////
////  eth_rxethmac.v                                              ////
////                                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects,ethmac/                   ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////  All additional information is avaliable in the Readme.txt   ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2011 Authors                                   ////
//// Copyright (C) 2001, 2011 Authors                             ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
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//
//
 
 
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
                     HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
                     ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
                     CrcError, StateIdle, StatePreamble, StateSFD, StateData,
 
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
 
                     PassAll, ControlFrmAddressOK
                    );
                    );
 
 
 
 
 
 
input         MRxClk;
input         MRxClk;
input         MRxDV;
input         MRxDV;
input   [3:0] MRxD;
input   [3:0] MRxD;
input         Transmitting;
input         Transmitting;
input         HugEn;
input         HugEn;
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assign MRxDEqD = MRxD == 4'hd;
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
assign MRxDEq5 = MRxD == 4'h5;
 
 
 
 
// Rx State Machine module
// Rx State Machine module
eth_rxstatem
eth_rxstatem rxstatem1
rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
  (.MRxClk(MRxClk),
                        .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
   .Reset(Reset),
                        .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
   .MRxDV(MRxDV),
                        .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
   .ByteCntEq0(ByteCntEq0),
                        .StateSFD(StateSFD), .StateDrop(StateDrop)
   .ByteCntGreat2(ByteCntGreat2),
 
   .Transmitting(Transmitting),
 
   .MRxDEq5(MRxDEq5),
 
   .MRxDEqD(MRxDEqD),
 
   .IFGCounterEq24(IFGCounterEq24),
 
   .ByteCntMaxFrame(ByteCntMaxFrame),
 
   .StateData(StateData),
 
   .StateIdle(StateIdle),
 
   .StatePreamble(StatePreamble),
 
   .StateSFD(StateSFD),
 
   .StateDrop(StateDrop)
                       );
                       );
 
 
 
 
// Rx Counters module
// Rx Counters module
eth_rxcounters
eth_rxcounters rxcounters1
rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
  (.MRxClk(MRxClk),
                            .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
   .Reset(Reset),
                            .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
   .MRxDV(MRxDV),
                            .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
   .StateIdle(StateIdle),
                            .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
   .StateSFD(StateSFD),
                            .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
   .StateData(StateData),
                            .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
   .StateDrop(StateDrop),
                            .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
   .StatePreamble(StatePreamble),
                            .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
   .MRxDEqD(MRxDEqD),
 
   .DlyCrcEn(DlyCrcEn),
 
   .DlyCrcCnt(DlyCrcCnt),
 
   .Transmitting(Transmitting),
 
   .MaxFL(MaxFL),
 
   .r_IFG(r_IFG),
 
   .HugEn(HugEn),
 
   .IFGCounterEq24(IFGCounterEq24),
 
   .ByteCntEq0(ByteCntEq0),
 
   .ByteCntEq1(ByteCntEq1),
 
   .ByteCntEq2(ByteCntEq2),
 
   .ByteCntEq3(ByteCntEq3),
 
   .ByteCntEq4(ByteCntEq4),
 
   .ByteCntEq5(ByteCntEq5),
 
   .ByteCntEq6(ByteCntEq6),
 
   .ByteCntEq7(ByteCntEq7),
 
   .ByteCntGreat2(ByteCntGreat2),
 
   .ByteCntSmall7(ByteCntSmall7),
 
   .ByteCntMaxFrame(ByteCntMaxFrame),
                            .ByteCntOut(ByteCnt)
                            .ByteCntOut(ByteCnt)
                           );
                           );
 
 
// Rx Address Check
// Rx Address Check
 
 
eth_rxaddrcheck
eth_rxaddrcheck rxaddrcheck1
rxaddrcheck1
  (.MRxClk(MRxClk),
              (.MRxClk(MRxClk),         .Reset( Reset),             .RxData(RxData),
   .Reset( Reset),
               .Broadcast (Broadcast),  .r_Bro (r_Bro),             .r_Pro(r_Pro),
   .RxData(RxData),
               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),    .ByteCntEq2(ByteCntEq2),
   .Broadcast (Broadcast),
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4),    .ByteCntEq5(ByteCntEq5),
   .r_Bro (r_Bro),
               .HASH0(r_HASH0),         .HASH1(r_HASH1),            .ByteCntEq0(ByteCntEq0),
   .r_Pro(r_Pro),
               .CrcHash(CrcHash),       .CrcHashGood(CrcHashGood),  .StateData(StateData),
   .ByteCntEq6(ByteCntEq6),
               .Multicast(Multicast),   .MAC(MAC),                  .RxAbort(RxAbort),
   .ByteCntEq7(ByteCntEq7),
               .RxEndFrm(RxEndFrm),     .AddressMiss(AddressMiss),  .PassAll(PassAll),
   .ByteCntEq2(ByteCntEq2),
 
   .ByteCntEq3(ByteCntEq3),
 
   .ByteCntEq4(ByteCntEq4),
 
   .ByteCntEq5(ByteCntEq5),
 
   .HASH0(r_HASH0),
 
   .HASH1(r_HASH1),
 
   .ByteCntEq0(ByteCntEq0),
 
   .CrcHash(CrcHash),
 
   .CrcHashGood(CrcHashGood),
 
   .StateData(StateData),
 
   .Multicast(Multicast),
 
   .MAC(MAC),
 
   .RxAbort(RxAbort),
 
   .RxEndFrm(RxEndFrm),
 
   .AddressMiss(AddressMiss),
 
   .PassAll(PassAll),
               .ControlFrmAddressOK(ControlFrmAddressOK)
               .ControlFrmAddressOK(ControlFrmAddressOK)
              );
              );
 
 
 
 
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
 
                        DlyCrcCnt[3:0] < 4'h9;
 
 
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
assign Data_Crc[3] = MRxD[0];
 
 
 
 
// Connecting module Crc
// Connecting module Crc
eth_crc
eth_crc crcrx
crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
  (.Clk(MRxClk),
               .Crc(Crc), .CrcError(CrcError)
   .Reset(Reset),
 
   .Data(Data_Crc),
 
   .Enable(Enable_Crc),
 
   .Initialize(Initialize_Crc),
 
   .Crc(Crc),
 
   .CrcError(CrcError)
              );
              );
 
 
 
 
 
 
// Latching CRC for use in the hash table
// Latching CRC for use in the hash table
 
 
always @ (posedge MRxClk)
always @ (posedge MRxClk)
begin
begin
  CrcHashGood <=  StateData[0] & ByteCntEq6;
  CrcHashGood <=  StateData[0] & ByteCntEq6;
end
end
 
 
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  else
  else
  if(StateData[0] & ByteCntEq6)
  if(StateData[0] & ByteCntEq6)
    CrcHash[5:0] <=  Crc[31:26];
    CrcHash[5:0] <=  Crc[31:26];
end
end
 
 
 
 
// Output byte stream
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
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      LatchedByte[7:0]   <=  8'h0;
      LatchedByte[7:0]   <=  8'h0;
      RxData[7:0]        <=  8'h0;
      RxData[7:0]        <=  8'h0;
    end
    end
  else
  else
    begin
    begin
      LatchedByte[7:0]   <=  {MRxD[3:0], LatchedByte[7:4]};  // Latched byte
      // Latched byte
 
      LatchedByte[7:0]   <=  {MRxD[3:0], LatchedByte[7:4]};
      DelayData          <=  StateData[0];
      DelayData          <=  StateData[0];
 
 
      if(GenerateRxValid)
      if(GenerateRxValid)
        RxData_d[7:0] <=  LatchedByte[7:0] & {8{|StateData}};  // Data goes through only in data state 
        // Data goes through only in data state 
 
        RxData_d[7:0] <=  LatchedByte[7:0] & {8{|StateData}};
      else
      else
      if(~DelayData)
      if(~DelayData)
        RxData_d[7:0] <=  8'h0;                                // Delaying data to be valid for two cycles. Zero when not active.
        // Delaying data to be valid for two cycles.
 
        // Zero when not active.
 
        RxData_d[7:0] <=  8'h0;
 
 
      RxData[7:0] <=  RxData_d[7:0];                           // Output data byte
      RxData[7:0] <=  RxData_d[7:0];                           // Output data byte
    end
    end
end
end
 
 
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      RxValid   <=  RxValid_d;
      RxValid   <=  RxValid_d;
    end
    end
end
end
 
 
 
 
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
assign GenerateRxStartFrm = StateData[0] &
 
                            ((ByteCntEq1 & ~DlyCrcEn) |
 
                            ((DlyCrcCnt == 4'h3) & DlyCrcEn));
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
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      RxStartFrm   <=  RxStartFrm_d;
      RxStartFrm   <=  RxStartFrm_d;
    end
    end
end
end
 
 
 
 
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign GenerateRxEndFrm = StateData[0] &
 
                          (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin

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