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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Revision 1.2 2001/09/11 14:17:00 mohor
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
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RxData, RxValid, RxStartFrm, RxEndFrm, CrcHash, CrcHashGood, Broadcast,
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RxData, RxValid, RxStartFrm, RxEndFrm, CrcHash, CrcHashGood, Broadcast,
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Multicast, ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
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Multicast, ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
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CrcError, StateIdle, StatePreamble, StateSFD, StateData
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CrcError, StateIdle, StatePreamble, StateSFD, StateData,
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MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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Line 95... |
input HugEn;
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input HugEn;
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input DlyCrcEn;
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input DlyCrcEn;
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input [15:0] MaxFL;
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input [15:0] MaxFL;
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input r_IFG;
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input r_IFG;
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input Reset;
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input Reset;
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input [47:0] MAC; // Station Address
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input r_Bro; // broadcast disable
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input r_Pro; // promiscuous enable
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input [31:0] r_HASH0; // lower 4 bytes Hash Table
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input [31:0] r_HASH1; // upper 4 bytes Hash Table
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output [7:0] RxData;
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output [7:0] RxData;
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output RxValid;
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output RxValid;
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output RxStartFrm;
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output RxStartFrm;
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output RxEndFrm;
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output RxEndFrm;
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output [8:0] CrcHash;
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output [8:0] CrcHash;
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Line 117... |
output CrcError;
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output CrcError;
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output StateIdle;
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output StateIdle;
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output StatePreamble;
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output StatePreamble;
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output StateSFD;
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output StateSFD;
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output [1:0] StateData;
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output [1:0] StateData;
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output RxAbort;
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reg [7:0] RxData;
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reg [7:0] RxData;
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reg RxValid;
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reg RxValid;
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reg RxStartFrm;
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reg RxStartFrm;
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reg RxEndFrm;
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reg RxEndFrm;
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Line 139... |
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wire MRxDEqD;
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wire MRxDEqD;
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wire MRxDEq5;
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wire MRxDEq5;
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wire StateDrop;
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wire StateDrop;
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wire ByteCntEq1;
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wire ByteCntEq1;
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wire ByteCntEq2;
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wire ByteCntEq3;
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wire ByteCntEq4;
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wire ByteCntEq5;
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wire ByteCntEq6;
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wire ByteCntEq6;
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wire ByteCntEq7;
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wire ByteCntSmall7;
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wire ByteCntSmall7;
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wire [31:0] Crc;
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wire [31:0] Crc;
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wire Enable_Crc;
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wire Enable_Crc;
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wire Initialize_Crc;
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wire Initialize_Crc;
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wire [3:0] Data_Crc;
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wire [3:0] Data_Crc;
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wire GenerateRxValid;
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wire GenerateRxValid;
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wire GenerateRxStartFrm;
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wire GenerateRxStartFrm;
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wire GenerateRxEndFrm;
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wire GenerateRxEndFrm;
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wire DribbleRxEndFrm;
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wire DribbleRxEndFrm;
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wire [3:0] DlyCrcCnt;
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wire [3:0] DlyCrcCnt;
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wire RxAbort;
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assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEqD = MRxD == 4'hd;
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assign MRxDEq5 = MRxD == 4'h5;
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assign MRxDEq5 = MRxD == 4'h5;
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eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
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eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
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.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
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.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
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.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
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.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
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.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
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.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
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.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
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.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
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.ByteCntEq1(ByteCntEq1), .ByteCntEq6(ByteCntEq6), .ByteCntGreat2(ByteCntGreat2),
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.ByteCntEq1(ByteCntEq1),
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.ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
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.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
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.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),.ByteCntGreat2(ByteCntGreat2),
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.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
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.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
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.ByteCnt(ByteCnt)
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.ByteCnt(ByteCnt)
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);
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);
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// Rx Address Check
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eth_rxaddrcheck rxaddrcheck1(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
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.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
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.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
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.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
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.HASH0(r_HASH0), .HASH1(r_HASH1),
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.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood),.StateData(StateData),
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.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
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.RxEndFrm(RxEndFrm)
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);
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assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
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assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
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assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
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assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
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Line 271... |
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
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if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
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Broadcast <= #Tp 1'b0;
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Broadcast <= #Tp 1'b0;
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else
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else
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if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
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if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
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Broadcast <= #Tp 1'b1;
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Broadcast <= #Tp 1'b1;
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else
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if(RxAbort | RxEndFrm)
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Broadcast <= #Tp 1'b0;
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end
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end
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end
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end
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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Line 287... |
else
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else
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begin
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begin
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if(Reset)
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if(Reset)
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Multicast <= #Tp 1'b0;
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Multicast <= #Tp 1'b0;
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else
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else
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if(StateData[0] & ByteCntEq1)
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if(StateData[0] & ByteCntEq1 & LatchedByte == 8'h01)
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Multicast <= #Tp LatchedByte[0];
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Multicast <= #Tp 1'b1;
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else if(RxAbort | RxEndFrm)
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Multicast <= #Tp 1'b0;
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end
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end
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end
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end
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assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
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assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
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