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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxstatem.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 88... Line 88...
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
                     IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
                     IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
                     StateDrop
                     StateDrop
                    );
                    );
 
 
parameter Tp = 1;
 
 
 
input         MRxClk;
input         MRxClk;
input         Reset;
input         Reset;
input         MRxDV;
input         MRxDV;
input         ByteCntEq0;
input         ByteCntEq0;
input         ByteCntGreat2;
input         ByteCntGreat2;
Line 142... Line 140...
// Rx State Machine
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      StateIdle     <= #Tp 1'b0;
      StateIdle     <=  1'b0;
      StateDrop     <= #Tp 1'b1;
      StateDrop     <=  1'b1;
      StatePreamble <= #Tp 1'b0;
      StatePreamble <=  1'b0;
      StateSFD      <= #Tp 1'b0;
      StateSFD      <=  1'b0;
      StateData0    <= #Tp 1'b0;
      StateData0    <=  1'b0;
      StateData1    <= #Tp 1'b0;
      StateData1    <=  1'b0;
    end
    end
  else
  else
    begin
    begin
      if(StartPreamble | StartSFD | StartDrop)
      if(StartPreamble | StartSFD | StartDrop)
        StateIdle <= #Tp 1'b0;
        StateIdle <=  1'b0;
      else
      else
      if(StartIdle)
      if(StartIdle)
        StateIdle <= #Tp 1'b1;
        StateIdle <=  1'b1;
 
 
      if(StartIdle)
      if(StartIdle)
        StateDrop <= #Tp 1'b0;
        StateDrop <=  1'b0;
      else
      else
      if(StartDrop)
      if(StartDrop)
        StateDrop <= #Tp 1'b1;
        StateDrop <=  1'b1;
 
 
      if(StartSFD | StartIdle | StartDrop)
      if(StartSFD | StartIdle | StartDrop)
        StatePreamble <= #Tp 1'b0;
        StatePreamble <=  1'b0;
      else
      else
      if(StartPreamble)
      if(StartPreamble)
        StatePreamble <= #Tp 1'b1;
        StatePreamble <=  1'b1;
 
 
      if(StartPreamble | StartIdle | StartData0 | StartDrop)
      if(StartPreamble | StartIdle | StartData0 | StartDrop)
        StateSFD <= #Tp 1'b0;
        StateSFD <=  1'b0;
      else
      else
      if(StartSFD)
      if(StartSFD)
        StateSFD <= #Tp 1'b1;
        StateSFD <=  1'b1;
 
 
      if(StartIdle | StartData1 | StartDrop)
      if(StartIdle | StartData1 | StartDrop)
        StateData0 <= #Tp 1'b0;
        StateData0 <=  1'b0;
      else
      else
      if(StartData0)
      if(StartData0)
        StateData0 <= #Tp 1'b1;
        StateData0 <=  1'b1;
 
 
      if(StartIdle | StartData0 | StartDrop)
      if(StartIdle | StartData0 | StartDrop)
        StateData1 <= #Tp 1'b0;
        StateData1 <=  1'b0;
      else
      else
      if(StartData1)
      if(StartData1)
        StateData1 <= #Tp 1'b1;
        StateData1 <=  1'b1;
    end
    end
end
end
 
 
assign StateData[1:0] = {StateData1, StateData0};
assign StateData[1:0] = {StateData1, StateData0};
 
 

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