URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 304 and 306

Rev 304	Rev 306
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.7 2003/11/12 18:24:59 tadejm`
	`// WISHBONE slave changed and tested from only 32-bit accesss to byte access.`
	`//`
`// Revision 1.6 2003/10/17 07:46:15 markom`	`// Revision 1.6 2003/10/17 07:46:15 markom`
`// mbist signals updated according to newest convention`	`// mbist signals updated according to newest convention`
`//`	`//`
`// Revision 1.5 2003/08/14 16:42:58 simons`	`// Revision 1.5 2003/08/14 16:42:58 simons`
`// Artisan ram instance added.`	`// Artisan ram instance added.`
Line 178...	Line 181...
`vs_hdsp_256x32_bw ram0`	`vs_hdsp_256x32_bw ram0`
`endif	`endif
`(`	`(`
`.CK (clk),`	`.CK (clk),`
`.CEN (!ce),`	`.CEN (!ce),`
`.WEN (!we),`	`.WEN (~we),`
`.OEN (!oe),`	`.OEN (!oe),`
`.ADR (addr),`	`.ADR (addr),`
`.DI (di),`	`.DI (di),`
`.DOUT (do)`	`.DOUT (do)`

Line 206...	Line 209...
`art_hssp_256x32_bw ram0`	`art_hssp_256x32_bw ram0`
`endif	`endif
`(`	`(`
`.CLK (clk),`	`.CLK (clk),`
`.CEN (!ce),`	`.CEN (!ce),`
`.WEN (!we),`	`.WEN (~we),`
`.OEN (!oe),`	`.OEN (!oe),`
`.A (addr),`	`.A (addr),`
`.D (di),`	`.D (di),`
`.Q (do)`	`.Q (do)`