OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 352 and 354

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 352 Rev 354
Line 100... Line 100...
        input           oe;   // Output enable input, active high
        input           oe;   // Output enable input, active high
        input  [7:0]    addr; // address bus inputs
        input  [7:0]    addr; // address bus inputs
        input  [31:0]   di;   // input data bus
        input  [31:0]   di;   // input data bus
        output [31:0]   do;   // output data bus
        output [31:0]   do;   // output data bus
 
 
 
 
`ifdef ETH_BIST
`ifdef ETH_BIST
  input   mbist_si_i;       // bist scan serial in
  input   mbist_si_i;       // bist scan serial in
  output  mbist_so_o;       // bist scan serial out
  output  mbist_so_o;       // bist scan serial out
  input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
  input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif
`endif
Line 269... Line 268...
        // RAM read and write
        // RAM read and write
        //
        //
 
 
        // read operation
        // read operation
        always@(posedge clk)
        always@(posedge clk)
          if (ce) // && !we)
     if (ce)
                raddr <=  addr; // read address needs to be registered to read clock
                raddr <=  addr; // read address needs to be registered to read clock
 
 
        assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
   assign  q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
 
 
        // write operation
        // write operation
        always@(posedge clk)
        always@(posedge clk)
        begin
        begin
                if (ce && we[3])
                if (ce && we[3])

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.