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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 352 and 354
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| Rev 352 |
Rev 354 |
| Line 100... |
Line 100... |
input oe; // Output enable input, active high
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input oe; // Output enable input, active high
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input [7:0] addr; // address bus inputs
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input [7:0] addr; // address bus inputs
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input [31:0] di; // input data bus
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input [31:0] di; // input data bus
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output [31:0] do; // output data bus
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output [31:0] do; // output data bus
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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input mbist_si_i; // bist scan serial in
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input mbist_si_i; // bist scan serial in
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output mbist_so_o; // bist scan serial out
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output mbist_so_o; // bist scan serial out
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input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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`endif
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`endif
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Line 268... |
// RAM read and write
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// RAM read and write
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//
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//
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// read operation
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// read operation
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always@(posedge clk)
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always@(posedge clk)
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if (ce) // && !we)
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if (ce)
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raddr <= addr; // read address needs to be registered to read clock
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raddr <= addr; // read address needs to be registered to read clock
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assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
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assign q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
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// write operation
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// write operation
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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if (ce && we[3])
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if (ce && we[3])
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