URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 356 and 357
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 356 |
Rev 357 |
Line 271... |
Line 271... |
// read operation
|
// read operation
|
always@(posedge clk)
|
always@(posedge clk)
|
if (ce)
|
if (ce)
|
raddr <= addr; // read address needs to be registered to read clock
|
raddr <= addr; // read address needs to be registered to read clock
|
|
|
assign q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
|
assign q = rst ? {32{1'b0}} : {mem3[raddr],
|
|
mem2[raddr],
|
|
mem1[raddr],
|
|
mem0[raddr]};
|
|
|
// write operation
|
// write operation
|
always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ce && we[3])
|
if (ce && we[3])
|
Line 293... |
Line 296... |
task print_ram;
|
task print_ram;
|
input [7:0] start;
|
input [7:0] start;
|
input [7:0] finish;
|
input [7:0] finish;
|
integer rnum;
|
integer rnum;
|
begin
|
begin
|
for (rnum=start;rnum<=finish;rnum=rnum+1)
|
for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1)
|
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
|
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
|
end
|
end
|
endtask
|
endtask
|
|
|
`endif // !ETH_ALTERA_ALTSYNCRAM
|
`endif // !ETH_ALTERA_ALTSYNCRAM
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.