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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 356 and 357
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| Rev 356 |
Rev 357 |
| Line 271... |
Line 271... |
// read operation
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// read operation
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always@(posedge clk)
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always@(posedge clk)
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if (ce)
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if (ce)
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raddr <= addr; // read address needs to be registered to read clock
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raddr <= addr; // read address needs to be registered to read clock
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assign q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
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assign q = rst ? {32{1'b0}} : {mem3[raddr],
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mem2[raddr],
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mem1[raddr],
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mem0[raddr]};
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// write operation
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// write operation
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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if (ce && we[3])
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if (ce && we[3])
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| Line 293... |
Line 296... |
task print_ram;
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task print_ram;
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input [7:0] start;
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input [7:0] start;
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input [7:0] finish;
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input [7:0] finish;
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integer rnum;
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integer rnum;
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begin
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begin
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for (rnum=start;rnum<=finish;rnum=rnum+1)
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for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1)
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$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
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$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
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end
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end
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endtask
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endtask
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`endif // !ETH_ALTERA_ALTSYNCRAM
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`endif // !ETH_ALTERA_ALTSYNCRAM
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