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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 86... Line 86...
                            TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
                            TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
                            TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
                            TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
                            ControlData, WillSendControlFrame, BlockTxDone
                            ControlData, WillSendControlFrame, BlockTxDone
                           );
                           );
 
 
parameter Tp = 1;
 
 
 
 
 
input         MTxClk;
input         MTxClk;
input         TxReset;
input         TxReset;
input         TxUsedDataIn;
input         TxUsedDataIn;
input         TxUsedDataOut;
input         TxUsedDataOut;
Line 137... Line 135...
 
 
// A command for Sending the control frame is active (latched)
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    WillSendControlFrame <= #Tp 1'b0;
    WillSendControlFrame <=  1'b0;
  else
  else
  if(TxCtrlEndFrm & CtrlMux)
  if(TxCtrlEndFrm & CtrlMux)
    WillSendControlFrame <= #Tp 1'b0;
    WillSendControlFrame <=  1'b0;
  else
  else
  if(TPauseRq & TxFlow)
  if(TPauseRq & TxFlow)
    WillSendControlFrame <= #Tp 1'b1;
    WillSendControlFrame <=  1'b1;
end
end
 
 
 
 
// Generation of the transmit control packet start frame
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    TxCtrlStartFrm <= #Tp 1'b0;
    TxCtrlStartFrm <=  1'b0;
  else
  else
  if(TxUsedDataIn_q & CtrlMux)
  if(TxUsedDataIn_q & CtrlMux)
    TxCtrlStartFrm <= #Tp 1'b0;
    TxCtrlStartFrm <=  1'b0;
  else
  else
  if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
  if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
    TxCtrlStartFrm <= #Tp 1'b1;
    TxCtrlStartFrm <=  1'b1;
end
end
 
 
 
 
 
 
// Generation of the transmit control packet end frame
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    TxCtrlEndFrm <= #Tp 1'b0;
    TxCtrlEndFrm <=  1'b0;
  else
  else
  if(ControlEnd | ControlEnd_q)
  if(ControlEnd | ControlEnd_q)
    TxCtrlEndFrm <= #Tp 1'b1;
    TxCtrlEndFrm <=  1'b1;
  else
  else
    TxCtrlEndFrm <= #Tp 1'b0;
    TxCtrlEndFrm <=  1'b0;
end
end
 
 
 
 
// Generation of the multiplexer signal (controls muxes for switching between
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    CtrlMux <= #Tp 1'b0;
    CtrlMux <=  1'b0;
  else
  else
  if(WillSendControlFrame & ~TxUsedDataOut)
  if(WillSendControlFrame & ~TxUsedDataOut)
    CtrlMux <= #Tp 1'b1;
    CtrlMux <=  1'b1;
  else
  else
  if(TxDoneIn)
  if(TxDoneIn)
    CtrlMux <= #Tp 1'b0;
    CtrlMux <=  1'b0;
end
end
 
 
 
 
 
 
// Generation of the Sending Control Frame signal (enables padding and CRC)
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    SendingCtrlFrm <= #Tp 1'b0;
    SendingCtrlFrm <=  1'b0;
  else
  else
  if(WillSendControlFrame & TxCtrlStartFrm)
  if(WillSendControlFrame & TxCtrlStartFrm)
    SendingCtrlFrm <= #Tp 1'b1;
    SendingCtrlFrm <=  1'b1;
  else
  else
  if(TxDoneIn)
  if(TxDoneIn)
    SendingCtrlFrm <= #Tp 1'b0;
    SendingCtrlFrm <=  1'b0;
end
end
 
 
 
 
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    TxUsedDataIn_q <= #Tp 1'b0;
    TxUsedDataIn_q <=  1'b0;
  else
  else
    TxUsedDataIn_q <= #Tp TxUsedDataIn;
    TxUsedDataIn_q <=  TxUsedDataIn;
end
end
 
 
 
 
 
 
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    BlockTxDone <= #Tp 1'b0;
    BlockTxDone <=  1'b0;
  else
  else
  if(TxCtrlStartFrm)
  if(TxCtrlStartFrm)
    BlockTxDone <= #Tp 1'b1;
    BlockTxDone <=  1'b1;
  else
  else
  if(TxStartFrmIn)
  if(TxStartFrmIn)
    BlockTxDone <= #Tp 1'b0;
    BlockTxDone <=  1'b0;
end
end
 
 
 
 
always @ (posedge MTxClk)
always @ (posedge MTxClk)
begin
begin
  ControlEnd_q     <= #Tp ControlEnd;
  ControlEnd_q     <=  ControlEnd;
  TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
  TxCtrlStartFrm_q <=  TxCtrlStartFrm;
end
end
 
 
 
 
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn &  ~DlyCrcCnt[2];
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn &  ~DlyCrcCnt[2];
 
 
 
 
// Delayed CRC counter
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    DlyCrcCnt <= #Tp 4'h0;
    DlyCrcCnt <=  4'h0;
  else
  else
  if(ResetByteCnt)
  if(ResetByteCnt)
    DlyCrcCnt <= #Tp 4'h0;
    DlyCrcCnt <=  4'h0;
  else
  else
  if(IncrementDlyCrcCnt)
  if(IncrementDlyCrcCnt)
    DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
    DlyCrcCnt <=  DlyCrcCnt + 1'b1;
end
end
 
 
 
 
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
Line 263... Line 261...
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    ByteCnt <= #Tp 6'h0;
    ByteCnt <=  6'h0;
  else
  else
  if(ResetByteCnt)
  if(ResetByteCnt)
    ByteCnt <= #Tp 6'h0;
    ByteCnt <=  6'h0;
  else
  else
  if(IncrementByteCntBy2 & EnableCnt)
  if(IncrementByteCntBy2 & EnableCnt)
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
    ByteCnt <=  (ByteCnt[5:0] ) + 2'h2;
  else
  else
  if(IncrementByteCnt & EnableCnt)
  if(IncrementByteCnt & EnableCnt)
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
    ByteCnt <=  (ByteCnt[5:0] ) + 1'b1;
end
end
 
 
 
 
assign ControlEnd = ByteCnt[5:0] == 6'h22;
assign ControlEnd = ByteCnt[5:0] == 6'h22;
 
 
Line 313... Line 311...
 
 
// Latched Control data
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
always @ (posedge MTxClk or posedge TxReset)
begin
begin
  if(TxReset)
  if(TxReset)
    ControlData[7:0] <= #Tp 8'h0;
    ControlData[7:0] <=  8'h0;
  else
  else
  if(~ByteCnt[0])
  if(~ByteCnt[0])
    ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
    ControlData[7:0] <=  MuxedCtrlData[7:0];
end
end
 
 
 
 
 
 
endmodule
endmodule

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