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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Diff between revs 352 and 353

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Rev 352 Rev 353
Line 248... Line 248...
  else
  else
  if(ResetByteCnt)
  if(ResetByteCnt)
    DlyCrcCnt <=  4'h0;
    DlyCrcCnt <=  4'h0;
  else
  else
  if(IncrementDlyCrcCnt)
  if(IncrementDlyCrcCnt)
    DlyCrcCnt <=  DlyCrcCnt + 1'b1;
    DlyCrcCnt <=  DlyCrcCnt + 4'd1;
end
end
 
 
 
 
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
Line 267... Line 267...
  else
  else
  if(ResetByteCnt)
  if(ResetByteCnt)
    ByteCnt <=  6'h0;
    ByteCnt <=  6'h0;
  else
  else
  if(IncrementByteCntBy2 & EnableCnt)
  if(IncrementByteCntBy2 & EnableCnt)
    ByteCnt <=  (ByteCnt[5:0] ) + 2'h2;
    ByteCnt <=  (ByteCnt[5:0] ) + 6'd2;
  else
  else
  if(IncrementByteCnt & EnableCnt)
  if(IncrementByteCnt & EnableCnt)
    ByteCnt <=  (ByteCnt[5:0] ) + 1'b1;
    ByteCnt <=  (ByteCnt[5:0] ) + 6'd1;
end
end
 
 
 
 
assign ControlEnd = ByteCnt[5:0] == 6'h22;
assign ControlEnd = ByteCnt[5:0] == 6'h22;
 
 

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