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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txcounters.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 90... Line 90...
                       StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
                       StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
                       ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
                       ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
                       ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
                       ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
                      );
                      );
 
 
parameter Tp = 1;
 
 
 
input MTxClk;             // Tx clock
input MTxClk;             // Tx clock
input Reset;              // Reset
input Reset;              // Reset
input StatePreamble;      // Preamble state
input StatePreamble;      // Preamble state
input StateIPG;           // IPG state
input StateIPG;           // IPG state
input [1:0] StateData;    // Data state
input [1:0] StateData;    // Data state
Line 150... Line 148...
 
 
// Nibble Counter
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    NibCnt <= #Tp 16'h0;
    NibCnt <=  16'h0;
  else
  else
    begin
    begin
      if(ResetNibCnt)
      if(ResetNibCnt)
        NibCnt <= #Tp 16'h0;
        NibCnt <=  16'h0;
      else
      else
      if(IncrementNibCnt)
      if(IncrementNibCnt)
        NibCnt <= #Tp NibCnt + 1'b1;
        NibCnt <=  NibCnt + 1'b1;
     end
     end
end
end
 
 
 
 
assign NibCntEq7   = &NibCnt[2:0];
assign NibCntEq7   = &NibCnt[2:0];
Line 182... Line 180...
 
 
// Transmit Byte Counter
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ByteCnt[15:0] <= #Tp 16'h0;
    ByteCnt[15:0] <=  16'h0;
  else
  else
    begin
    begin
      if(ResetByteCnt)
      if(ResetByteCnt)
        ByteCnt[15:0] <= #Tp 16'h0;
        ByteCnt[15:0] <=  16'h0;
      else
      else
      if(IncrementByteCnt)
      if(IncrementByteCnt)
        ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
        ByteCnt[15:0] <=  ByteCnt[15:0] + 1'b1;
    end
    end
end
end
 
 
 
 
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
Line 203... Line 201...
 
 
// Delayed CRC counter
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    DlyCrcCnt <= #Tp 3'h0;
    DlyCrcCnt <=  3'h0;
  else
  else
    begin
    begin
      if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
      if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
        DlyCrcCnt <= #Tp 3'h0;
        DlyCrcCnt <=  3'h0;
      else
      else
      if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
      if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
        DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
        DlyCrcCnt <=  DlyCrcCnt + 1'b1;
    end
    end
end
end
 
 
 
 
 
 

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