//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_txcounters.v ////
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//// eth_txcounters.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/04/22 14:54:14 mohor
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// Revision 1.5 2002/04/22 14:54:14 mohor
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// FCS should not be included in NibbleMinFl.
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// FCS should not be included in NibbleMinFl.
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//
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//
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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// Link in the header changed.
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//
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Few little NCSIM warnings fixed.
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// Few little NCSIM warnings fixed.
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//
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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// is done due to the ASIC tools.
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//
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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//
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//
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// Revision 1.4 2001/06/27 21:27:45 mohor
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// Revision 1.4 2001/06/27 21:27:45 mohor
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// Few typos fixed.
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// Few typos fixed.
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//
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//
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// Revision 1.2 2001/06/19 10:38:07 mohor
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// Revision 1.2 2001/06/19 10:38:07 mohor
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// Minor changes in header.
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// Minor changes in header.
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//
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//
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// Revision 1.1 2001/06/19 10:27:57 mohor
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// Revision 1.1 2001/06/19 10:27:57 mohor
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// TxEthMAC initial release.
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// TxEthMAC initial release.
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
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module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
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StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
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StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
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StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
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StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
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ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
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ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
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ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
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ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
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);
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);
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input MTxClk; // Tx clock
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input MTxClk; // Tx clock
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input Reset; // Reset
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input Reset; // Reset
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input StatePreamble; // Preamble state
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input StatePreamble; // Preamble state
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input StateIPG; // IPG state
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input StateIPG; // IPG state
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input [1:0] StateData; // Data state
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input [1:0] StateData; // Data state
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input StatePAD; // PAD state
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input StatePAD; // PAD state
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input StateFCS; // FCS state
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input StateFCS; // FCS state
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input StateJam; // Jam state
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input StateJam; // Jam state
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input StateBackOff; // Backoff state
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input StateBackOff; // Backoff state
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input StateDefer; // Defer state
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input StateDefer; // Defer state
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input StateIdle; // Idle state
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input StateIdle; // Idle state
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input StateSFD; // SFD state
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input StateSFD; // SFD state
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input StartDefer; // Defer state will be activated in next clock
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input StartDefer; // Defer state will be activated in next clock
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input StartIPG; // IPG state will be activated in next clock
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input StartIPG; // IPG state will be activated in next clock
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input StartFCS; // FCS state will be activated in next clock
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input StartFCS; // FCS state will be activated in next clock
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input StartJam; // Jam state will be activated in next clock
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input StartJam; // Jam state will be activated in next clock
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input StartBackoff; // Backoff state will be activated in next clock
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input StartBackoff; // Backoff state will be activated in next clock
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input TxStartFrm; // Tx start frame
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input TxStartFrm; // Tx start frame
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input [15:0] MinFL; // Minimum frame length (in bytes)
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input [15:0] MinFL; // Minimum frame length (in bytes)
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input [15:0] MaxFL; // Miximum frame length (in bytes)
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input [15:0] MaxFL; // Miximum frame length (in bytes)
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input HugEn; // Pakets bigger then MaxFL enabled
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input HugEn; // Pakets bigger then MaxFL enabled
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input ExDfrEn; // Excessive deferral enabled
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input ExDfrEn; // Excessive deferral enabled
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input PacketFinished_q;
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input PacketFinished_q;
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input DlyCrcEn; // Delayed CRC enabled
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input DlyCrcEn; // Delayed CRC enabled
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output [15:0] ByteCnt; // Byte counter
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output [15:0] ByteCnt; // Byte counter
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output [15:0] NibCnt; // Nibble counter
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output [15:0] NibCnt; // Nibble counter
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output ExcessiveDefer; // Excessive Deferral occuring
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output ExcessiveDefer; // Excessive Deferral occuring
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output NibCntEq7; // Nibble counter is equal to 7
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output NibCntEq7; // Nibble counter is equal to 7
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output NibCntEq15; // Nibble counter is equal to 15
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output NibCntEq15; // Nibble counter is equal to 15
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output MaxFrame; // Maximum frame occured
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output MaxFrame; // Maximum frame occured
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output NibbleMinFl; // Nibble counter is greater than the minimum frame length
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output NibbleMinFl; // Nibble counter is greater than the minimum frame length
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output [2:0] DlyCrcCnt; // Delayed CRC Count
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output [2:0] DlyCrcCnt; // Delayed CRC Count
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wire ExcessiveDeferCnt;
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wire ExcessiveDeferCnt;
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wire ResetNibCnt;
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wire ResetNibCnt;
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wire IncrementNibCnt;
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wire IncrementNibCnt;
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wire ResetByteCnt;
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wire ResetByteCnt;
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wire IncrementByteCnt;
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wire IncrementByteCnt;
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wire ByteCntMax;
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wire ByteCntMax;
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reg [15:0] NibCnt;
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reg [15:0] NibCnt;
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reg [15:0] ByteCnt;
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reg [15:0] ByteCnt;
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reg [2:0] DlyCrcCnt;
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reg [2:0] DlyCrcCnt;
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assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
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assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
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| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
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| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
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assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
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assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
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| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
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| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
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// Nibble Counter
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// Nibble Counter
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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NibCnt <= 16'h0;
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NibCnt <= 16'h0;
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else
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else
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begin
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begin
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if(ResetNibCnt)
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if(ResetNibCnt)
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NibCnt <= 16'h0;
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NibCnt <= 16'h0;
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else
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else
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if(IncrementNibCnt)
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if(IncrementNibCnt)
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NibCnt <= NibCnt + 1'b1;
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NibCnt <= NibCnt + 16'd1;
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end
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end
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end
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end
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assign NibCntEq7 = &NibCnt[2:0];
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assign NibCntEq7 = &NibCnt[2:0];
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assign NibCntEq15 = &NibCnt[3:0];
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assign NibCntEq15 = &NibCnt[3:0];
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assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
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assign NibbleMinFl = NibCnt >= (((MinFL-16'd4)<<1) -1); // FCS should not be included in NibbleMinFl
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assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
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assign ExcessiveDeferCnt = NibCnt[13:0] == 14'h17b7;
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assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
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assign ExcessiveDefer = NibCnt[13:0] == 14'h17b7 & ~ExDfrEn; // 6071 nibbles
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assign IncrementByteCnt = StateData[1] & ~ByteCntMax
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assign IncrementByteCnt = StateData[1] & ~ByteCntMax
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| StateBackOff & (&NibCnt[6:0])
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| StateBackOff & (&NibCnt[6:0])
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| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
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| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
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assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
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assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
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// Transmit Byte Counter
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// Transmit Byte Counter
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ByteCnt[15:0] <= 16'h0;
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ByteCnt[15:0] <= 16'h0;
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else
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else
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begin
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begin
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if(ResetByteCnt)
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if(ResetByteCnt)
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ByteCnt[15:0] <= 16'h0;
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ByteCnt[15:0] <= 16'h0;
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else
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else
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if(IncrementByteCnt)
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if(IncrementByteCnt)
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ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
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ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
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end
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end
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end
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end
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assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
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assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
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assign ByteCntMax = &ByteCnt[15:0];
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assign ByteCntMax = &ByteCnt[15:0];
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// Delayed CRC counter
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// Delayed CRC counter
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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DlyCrcCnt <= 3'h0;
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DlyCrcCnt <= 3'h0;
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else
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else
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begin
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begin
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if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
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if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
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DlyCrcCnt <= 3'h0;
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DlyCrcCnt <= 3'h0;
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else
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else
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if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
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if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
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DlyCrcCnt <= DlyCrcCnt + 1'b1;
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DlyCrcCnt <= DlyCrcCnt + 3'd1;
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end
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end
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end
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end
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endmodule
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endmodule
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