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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/02/26 16:24:01 mohor
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// RetryCntLatched was unused and removed from design
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//
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// Revision 1.6 2002/02/22 12:56:35 mohor
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// Revision 1.6 2002/02/22 12:56:35 mohor
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// Retry is not activated when a Tx Underrun occured
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// Retry is not activated when a Tx Underrun occured
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//
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//
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// Revision 1.5 2002/02/11 09:18:22 mohor
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// Revision 1.5 2002/02/11 09:18:22 mohor
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// Tx status is written back to the BD.
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// Tx status is written back to the BD.
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Line 94... |
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
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module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
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Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
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Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
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IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
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IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
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MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
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MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
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ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
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ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
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LateCollision, StartDefer, StatePreamble, StateData
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LateCollision, DeferIndication, StatePreamble, StateData
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
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output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
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output StartTxDone;
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output StartTxDone;
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output StartTxAbort;
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output StartTxAbort;
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output MaxCollisionOccured;
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output MaxCollisionOccured;
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output LateCollision;
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output LateCollision;
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output StartDefer;
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output DeferIndication;
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output StatePreamble;
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output StatePreamble;
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output [1:0] StateData;
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output [1:0] StateData;
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reg [3:0] MTxD;
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reg [3:0] MTxD;
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reg MTxEn;
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reg MTxEn;
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Line 165... |
wire StartIPG;
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wire StartIPG;
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wire StartPreamble;
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wire StartPreamble;
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wire [1:0] StartData;
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wire [1:0] StartData;
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wire StartFCS;
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wire StartFCS;
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wire StartJam;
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wire StartJam;
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wire StartDefer;
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wire StartBackoff;
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wire StartBackoff;
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wire StateDefer;
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wire StateDefer;
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wire StateIPG;
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wire StateIPG;
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wire StateIdle;
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wire StateIdle;
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wire StatePAD;
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wire StatePAD;
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Line 199... |
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assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
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assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
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assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
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assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
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assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & ~Pad & ~CrcEn);
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assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
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assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
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assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
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assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
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assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
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| Line 448... |
Line 452... |
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
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.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
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.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
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.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
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.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
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.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
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.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
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.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
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.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
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.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
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.StartDefer(StartDefer), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
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.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
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);
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);
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wire Enable_Crc;
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wire Enable_Crc;
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wire [3:0] Data_Crc;
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wire [3:0] Data_Crc;
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